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p reliminary w741c20x 4-bit microcontroller publication release date: march 1998 - 1 - revision a3 table of contents-- general description ................................ ................................ ................................ .............................. 2 features ................................ ................................ ................................ ................................ ...................... 2 pin configuration ................................ ................................ ................................ ................................ .... 3 pin description ................................ ................................ ................................ ................................ .......... 4 block diagram ................................ ................................ ................................ ................................ ........... 5 functional description ................................ ................................ ................................ ........................ 6 absolute maximum ratings ................................ ................................ ................................ ................ 27 dc characteristics ................................ ................................ ................................ ............................... 28 ac characteristics ................................ ................................ ................................ ............................... 29 pad assignment & positions ................................ ................................ ................................ ............... 30 typical application circuit ................................ ................................ ................................ ................ 31 instruction set table ................................ ................................ ................................ .......................... 32 package dimensions ................................ ................................ ................................ .............................. 79
p reliminary w741c20x - 2 - general description the w741c20x is a high-performance 4-bit microcontroller ( m c) that operates on very low current. the device contains a 4-bit alu, two 8-bit timers, a divider, a serial port, and five 4-bit i/o ports (including 3 output ports for led driving). there are also seven interrupt sources and 8-level subroutine nesting for interrupt applications. the w741c20x has two power reduction modes, hold mode and stop mode, which help to minimize power dissipation. the w741c20x is suitable for remote controllers, toy controllers, keyboard controllers, speech synthesis lsi controllers, and other products. features operating voltage: 2.2v to 5.5v crystal or rc oscillation circuit can be selected by the code option - crystal/ceramic oscillator: up to 4 mhz - rc oscillator: up to 4 mhz both in crystal or rc oscillator operation mode, high-frequency (400 khz to 4 mhz) or low- frequency (32.768 khz) oscillation must be determined by the code option memory - 2048 x 16 bit program rom (including 2k x 4 bit look-up table) - 128 x 4 bit data ram (including 16 working registers) 21 input/output pins - input/output ports: 4 ports/16 pins - serial input/output port: 1 port /4 pins (high sink current for led driving) - mfp out put pin: 1 pin (mfp) power-down mode - hold function: no operation (except for oscillator) - stop function: no operation (including oscillator) seven types of interrupts - five internal interrupts (divider 0, timer 0, timer 1, and serial i/o) - two external interrupts (port rc and int pin) mfp output pin - output is software selectable as modulating or nonmodulating frequency - works as frequency output specified by timer 1 built-in 14-bit clock frequency divider circuit t wo built-in 8-bit programmable countdown timers - timer 0: one of two internal clock frequencies (f osc /4 or f osc /1024) can be selected - timer 1: offers auto-reload function, and one of two internal clock frequencies (f osc or f osc /64) can be selected, or falling edge of pin rc.0 can be selected (output through mfp pin) built-in 18/14-bit watchdog timer selectable for system reset
p reliminary w741c20x publication release date: march 1998 - 3 - revision a3 powerful instruction set: 118 instructions 8-level subroutine (include interrupt) nesting one serial transmission/ receiver port specified by software up to 1 m s instruction cycle (with 4 mhz operating frequency) packaged in 18-pin, 20-pin, 28-pin pdip and 20-pin, 28-pin sop pin configuration 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 rb3 rb2 rb1 ra1 ra0 xin xout rc3 rc2 rc1 res int ra3 ra2 rb0 rc0 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 re3 re2 re1 ra1 ra0 xin xout rd3 rd2 rd1 res int ra3 ra2 re0 rd0 19 10 rb0 rc3 16 17 18 11 12 13 rb3 rb2 rb1 rc2 rc1 rc0 15 14 nc mfp w741c201 w741c202/c205 18-pdip(300 mil) 28 skinny(300 mil), 28 sop v ss v dd v ss v dd 10 11 12 13 15 16 17 18 1 2 3 4 5 6 7 8 9 rb3 rb2 rb1 ra1 ra0 xin xout rc3 rc2 rc1 ra3 ra2 rb0 rc0 w741c203 20-pdip(300 mil) 14 19 20 10 11 12 13 15 16 17 18 1 2 3 4 5 6 7 8 9 rb3 rb2 rb1 ra1 ra0 xin xout rc3 rc2 rc1 res int ra3 ra2 rb0 rc0 w741c204 20 sop 14 19 20 int res v ss v ss v dd v dd v ss v ss v dd v dd
p reliminary w741c20x - 4 - pin description symbol i/o function xin i input pin for oscillator. connected to crystal or resistor to generate system clock by code option. xout o output pin for oscillator. connected to crystal or resistor to generate system clock by code option. ra0 - ra3 i/o input/output port. input/output mode specified by port mode 1 register (pm1). when used as output port, can provide high sink current for driving led. rb0 - rb3 i/o input/output port. input/output mode specified by port mode 2 register (pm2). when used as output port, can provide high sink current for driving led. rc0 - rc3 i/o input/output port. input/output mode specified by port mode 4 register (pm4). each pin has an independent interrupt capability in input mode. rd0 - rd3 i/o input/output port. input/output mode specified by port mode 5 register (pm5). re0/dout re1/clko re2/din re3/clki i/o special input/output port. this port can be configured by software to act as the output of internal port rt or the serial i/o port. when used as output port, can provide high sink current for driving led. mfp o output pin only. this pin can output modulating or nonmodulating frequency, or timer 1 clock output specified by mode register 1 (mr1). int i external interrupt pin with pull-high resistor. res i system reset pin with pull-high resistor. v dd i positive power supply (+). v ss i negative power supply (-).
p reliminary w741c20x publication release date: march 1998 - 5 - revision a3 block diagram xin xout pc stack (8 levels) ram (128*4) alu timer 0 (8-bit) timing generator port ra port rb modulation frequency pulse ra0 to 3 rb0 to 3 re0 to 3 mfp vdd vss rom (2048*16) (look_up table 2k*4) timer 1 (8-bit) acc res int divider 0 (14-bit) watchdog timer (4-bit) hcf pef hef ief central control unit evf sef psr0 . . mux sel +1(+2) . port rc rc0 to 3 port rd rd0 to 3 pr pm0 mr0 psr1 psr2 port rt serial i/o mux (re0/dout, re1/clko, re2/din, re3/clki) sel
p reliminary w741c20x - 6 - functional description program counter (pc) organized as an 11-bit binary counter (pc0 to pc10), the program counter generates the addresses of the 2048 16 on-chip rom containing the program instruction words. when jump or subroutine call instructions or interrupt, or initial reset conditions are to be executed, the address corresponding to the instruction will be loaded into the program counter. the format used is shown below. item address interrupt priority initial reset 000h - int 0 (divider) 004h 1st int 1 (timer 0) 008h 2nd int 2 (port rc) 00ch 3rd int 3 ( int pin) 014h 4th int 4 (serial port input) 018h 5th int 5 (serial port output) 01ch 6th int 6 (timer 1) 020h 7th jmp instruction xxxh - subroutine call xxxh - stack register (stack) the stack register is organized as 11 bits x 8 levels (first-in, last-out). when either a call subroutine or an interrupt is executed, the program counter will be pushed onto the stack register automatically. at the end of a call subroutine or an interrupt service subroutine, the rtn instruction must be executed to pop the contents of the stack register into the program counter. when the stack register is pushed over the eighth level, the contents of the first level will be lost. in other words, the stack register is always eight levels deep. program memory (rom) the read-only memory (rom) is used to store program codes; the look-up table is arranged as 2048 4 bits. the first three quarters of rom (000h to 5ffh) are used to store instruction codes only, but the last quarter (600h to 7ffh) can store both instruction codes and the look-up table. each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements. instruction movc r is used to read the look-up table and transfer table data to the ram. the organization of the program memory is shown in figure 1 .
p reliminary w741c20x publication release date: march 1998 - 7 - revision a3 3 2 1 0 7ffh 600h 2048 address 000h 16 bits 2048 x 16-bit acc tabl tabh rom address = 600h + offset/4 offset 0 1 1 x x x x x x x x x - x x x x x x x x x y y each element (4 bits) of the look-up table this area can be used to store both instruction code and look-up table figure 1 . program memory organization data memory (ram) 1. architecture the static data memory (ram) used to store data is arranged as 128 4 bits. the data memory can be addressed directly or indirectly. the organization of the data memory is shown in figure 2 . working register 128 address 00h 4 bits 128 x 4-bit 7fh : 0fh figure 2 . data memory organization
p reliminary w741c20x - 8 - the first sixteen addresses (00h to 0fh) in the data memory are known as the working registers (wr). the other data memory is used as general memory and cannot operate directly with immediate data. the relationship between data memory locations and the page register (page) in indirect addressing mode is described in the next section. 2. page register (page) the page register is organized as a 4-bit binary register. the bit descriptions are as follows: r/w r/w r/w 0 1 2 3 page note: r/w means read/write available. bit 3 is reserved. bit 2, bit 1, bit 0 indirect addressing mode preselect bits: 000 = page 0 (00h - 0fh) 001 = page 1 (10h - 1fh) 010 = page 2 (20h - 2fh) 011 = page 3 (30h - 3fh) 100 = page 4 (40h - 4fh) 101 = page 5 (50h - 5fh) 110 = page 6 (60h - 6fh) 111 = page 7 (70h - 7fh) accumulator (acc) the accumulator (acc) is a 4-bit register used to hold results from the alu and transfer data between the memory, i/o ports, and registers. arithmetic and logic unit (alu) this is a circuit which performs arithmetic and logic operations. the alu provides the following functions: logic operations: anl, xrl, orl branch decisions: jb0, jb1, jb2, jb3, jnz, jz, jc, jnc, dskz, dsknz, skb0, skb1, skb2, skb3 shift operations: shrc, rrc, shlc, rlc binary additions/subtractions: adc, sbc, add, sub, adu, dec, inc after any of the above instructions are executed, the status of the carry flag (cf) and zero flag (zf) is stored in the internal registers. cf can be read out by executing mova r, cf.
p reliminary w741c20x publication release date: march 1998 - 9 - revision a3 clock generator the w741c20x provides a crystal or rc oscillation circuit selected by option codes to generate the system clock through external connections. if a crystal oscillator is used, a crystal or a ceramic resonator must be connected to xin and xout, and the capacitor must be connected if an accurate frequency is needed. when a crystal oscillator is used, a high-frequency clock (400 khz to 4 mhz) or low-frequency clock (32 khz) can be selected for the system clock by means of option codes. if the rc oscillator is used, a resistor in the range of 20 k w to 1.6 m w must be connected to xin and xout, as shown in figure 3. the system clock frequency range is from 32 khz to 4 mhz. one machine cycle consists of a four-phase system clock sequence and can run up to 1 m s with a 4 mhz system clock. xin xout xin xout or crystal resistor 32 khz or 400k to 4mhz figure 3 . oscillator configuration divider 0 divider 0 is organized as a 14-bit binary up-counter designed to generate periodic interrupts, as shown in figure 4 . when the system starts, the divider is incremented by each system clock (f osc ). when an overflow occurs, the divider event flag is set to 1 (evf.0 = 1). then, if the divider interrupt enable flag has been set (ief.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (hef.0 = 1), the hold state is terminated. the last 4-stage of the divider 0 can be reset by executing clr divr0 instruction. if the oscillator is connected to the 32768 hz crystal, the evf.0 will be set to 1 periodically at each 500 ms interval. watchdog timer (wdt) the watchdog timer (wdt) is organized as a 4-bit up counter and is designed to protect the program from unknown errors. the wdt is enable when the corresponding option code bit of the wdt is set to 1. if the wdt overflows, the chip will be reset. at initial reset, the input clock of the wdt is f osc /1024. the input clock of the wdt can be switched to f osc /16384 (or f osc /1024) by executing the set pmf, #08h (or clr pmf, #08h) instruction. the contents of the wdt can be reset by the instruction clr wdt. in normal operation, the application program must reset wdt before it overflows. a wdt overflow indicates that the operation is not under control and the chip will be reset. the wdt minimun overflow period is 468.75 ms when the system clock (f osc ) is 32 khz and wdt clock input is f osc /1024. when the corresponding option code bit of the wdt is set to 0, the wdt function is disabled. the organization of the divider0 and watchdog timer is shown in figure 4.
p reliminary w741c20x - 10 - q1 q2 q9 q10 q11 q12 q14 q13 fosc s r q hef.0 ief.0 1. reset 2. clr evf, #01h evf.0 hold mode release (hcf.0) divider0 interrupt (int0) ... overflow signal wdt enable /disable pmf.3 fosc/1024 fosc/16384 mask option qw1 qw2 qw4 qw3 r r r r divider0 system reset 1. reset 2. clr wdt 3. clr divr0 r r r r figure 4 . organization of divider and watchdog timer parameter flag (pmf) the parameter flag is organized as a 4-bit binary register (pmf.0 to pmf.3). the pmf is controlled by the set pmf, #i or clr pmf, #i instruction. the bit descriptions are as follows: w 0 1 2 3 pmf note: w means write only. bit 0, bit 1 & bit 2 are reserved. bit 3 = 0 the fundamental frequency of the watch dog timer is f osc /1024. = 1 the fundamental frequency of the watch dog timer is f osc /16384. at initial reset, bit 3 of pmf is set to "0".
p reliminary w741c20x publication release date: march 1998 - 11 - revision a3 timer/counter timer 0 (tm0) timer 0 (tm0) is a programmable 8-bit binary down-counter. the specified value can be loaded into tm0 by executing the mov tm0l (tm0h), r or mov tm0, #i instruction. when the mov tm0l (tm0h), r instructions are executed, the tm0 will stop down-counting (if the tm0 is down-counting), the mr0.3 will be reset to 0, and the specified value is loaded into tm0. if mr0.3 is set to 1, the event flag 1 (evf.1) is reset and the tm0 starts to count. when it decrements to ffh, timer 0 stops operating and generates an underflow (evf.1 = 1). the interrupt is executed if the timer 0 interrupt enable flag has been set (ief.1 = 1); and the hold state is terminated if the hold release enable flag 1 has been set (hef.1 = 1). the timer 0 clock input can be set as f osc /1024 or f osc /4 by setting mr0.0 to 1 or by resetting mr0.0 to 0. the default timer value is f osc /4. the organization of timer 0 is shown in figure 5. if the timer 0 clock input is f osc /4, then: desired time 0 interval = (preset value +1) 4 1/f osc if the timer 0 clock input is f osc /1024, then: desired time 0 interval = (preset value +1) 1024 1/f osc preset value: decimal number of timer 0 preset value f osc : clock oscillation frequency fosc/4 fosc/1024 enable disable 1. reset 2. clr evf, #02h 8-bit binary down counter s r q hef.1 ief.1 hold mode release (hcf.1) timer 0 interrupt (int1) 1. reset 2. clr evf, #02h evf.1 mr0.0 (timer 0) 1. set mr0.3 to 1 2. mov tm0, #i 3. reset mr0.3 to 0 3. set mr0.3 to 1 4. mov tm0, #i 4 4 mov tm0h, r mov tm0l, r 4. mov tm0l, r or mov tm0h, r 8 mov tm0, #i figure 5 . organization of timer 0
p reliminary w741c20x - 12 - timer 1 (tm1) timer 1 (tm1) is also a programmable 8-bit binary down counter, as shown in figure 6 . timer 1 can be used as a counter to count external events or to output an arbitrary frequency to the mfp pin. the input clock of timer 1 can be one of three sources: fosc/64, fosc, or an external clock from the rc.0 input pin. the source can be selected by setting bit 0 and bit 1 of mode register 1 (mr1). at initial reset, the timer 1 clock input is fosc. if an external clock is selected as the clock source of timer 1, the content of timer 1 is decreased by 1 at the falling edge of rc.0. when the mov tm1l, r or mov tm1h,r instruction is executed, the specified data are loaded into the auto-reload buffer and the tm1 down-counting will be disabled (i.e. mr1.3 is reset to 0). if the bit 3 of mr1 is set (mr1.3 = 1), the contents of the auto-reload buffer will be loaded into the tm1 down counter, timer 1 starts to down count, and the event flag 7 is reset (evf.7 = 0). when the mov tm1, #i instruction is executed, the event flag 7 (evf.7) and mr1.3 are reset and the specified value is loaded into auto-reload buffer and tm1 by the internal hardware, then the mr1.3 is set, that is the tm1 starts to count by the hardware. when the timer decrements to ffh, it will generate an underflow (evf.7 = 1) and be auto-reloaded with the specified data, after which it will continue to count down. an interrupt is executed if the interrupt enable flag 7 has been set to 1 (ief.7 = 1), and the hold state is terminated if the hold mode release enable flag 7 is set to 1 (hef.7 = 1). the specified frequency of timer 1 can be delivered to the mfp output pin by programming bit 2 of mr1. bit 3 of mr1 can be used to make timer 1 stop or start counting. if the timer 1 clock input is f t, then : desired timer 1 interval = (preset value +1) / f t desired frequency for mfp output pin = f t ? (preset value + 1) ? 2 (hz) preset value: decimal number of timer 1 preset value, and f osc : clock oscillation frequency auto-reload buffer 8 bits mr1.1 external clock via rc.0 1. mr1.3 = 1 2. mov tm1, #i underflow signal evf.7 mfp mfp signal mr1.2 output pin 8-bit binary down counter 2 circuit reset reset disable enable fosc/64 fosc mr1.0 (timer 1) s r q 1. reset 2. int 7 accept 3. clr evf, #80h t f 1. mr1.3 = 0 4. set mr1.3 to 1 4 4 mov tm1h, r mov tm1l, r set mr1.3 to 1 mov tm1, #i 5. mov tm1, #i 8 mov tm1, #i figure 6 . organization of timer 1
p reliminary w741c20x publication release date: march 1998 - 13 - revision a3 for example, when f t equals 32768 hz, depending on the preset value of tm1, the mfp pin will output a single tone signal in the tone frequency range from 64 hz to 16384 hz. the relation between the tone frequency and the preset value of tm1 is shown in the table below. 3rd octave 4th octave 5th octave tone frequency tm1 preset value & mfp frequency tone frequency tm1 preset value & mfp frequency tone frequency tm1 preset value & mfp frequency c 130.81 7ch 131.07 261.63 3eh 260.06 523.25 1eh 528.51 c# 138.59 75h 138.84 277.18 3ah 277.69 554.37 1ch 564.96 t d 146.83 6fh 146.28 293.66 37h 292.57 587.33 1bh 585.14 d# 155.56 68h 156.03 311.13 34h 309.13 622.25 19h 630.15 o e 164.81 62h 165.49 329.63 31h 327.68 659.26 18h 655.36 f 174.61 5dh 174.30 349.23 2eh 372.36 698.46 16h 712.34 n f# 185.00 58h 184.09 369.99 2bh 390.09 739.99 15h 744.72 g 196.00 53h 195.04 392.00 29h 420.10 783.99 14h 780.19 e g# 207.65 4eh 207.39 415.30 26h 443.81 830.61 13h 819.20 a 220.00 49h 221.40 440.00 24h 442.81 880.00 12h 862.84 a# 233.08 45h 234.05 466.16 22h 468.11 932.23 11h 910.22 b 246.94 41h 248.24 493.88 20h 496.48 987.77 10h 963.76 note: central tone is a4 (440 hz). mode register 0 (mr0) mode register 0 is organized as a 4-bit binary register (mr0.0 to mr0.3). mr0 can be used to control the operation of timer 0. the bit descriptions are as follows: w w 0 1 2 3 mr0 note: w means write only. bit 0 = 0 the fundamental frequency of timer 0 is f osc /4. = 1 the fundamental frequency of timer 0 is f osc /1024. bit 1 & bit 2 are reserved bit 3 = 0 timer 0 stops down-counting. = 1 timer 0 starts down-counting.
p reliminary w741c20x - 14 - mode register 1 (mr1) mode register 1 is organized as a 4-bit binary register (mr1.0 to mr1.3). mr1 can be used to control the operation of timer 1. the bit descriptions are as follows: w w w w 0 1 2 3 mr1 note: w means write only. bit 0 = 0 the internal fundamental frequency of timer 1 is f osc . = 1 the internal fundamental frequency of timer 1 is f osc /64. bit 1 = 0 the fundamental frequency source of timer 1 is the internal clock. = 1 the fundamental frequency source of timer 1 is the external clock from rc.0 input pin. bit 2 = 0 the specified waveform of the mfp generator is delivered at the mfp output pin. = 1 the specified frequency of timer 1 is delivered at the mfp output pin. bit 3 = 0 timer 1 stops down-counting. = 1 timer 1 starts down-counting. input/output ports ra, rb port ra consists of pins ra.0 to ra.3 and port rb consists of pins rb.0 to rb.3. at initial reset, input/output ports ra and rb are both in input mode. when ra and rb are used as output ports, cmos or nmos open drain output type can be selected by the pm0 register. each pin of port ra or rb can be specified as input or output mode independently by the pm1 and pm2 registers. the mova r, ra or mova r, rb instructions operate the input functions and the mov ra, r or mov rb, r operate the output functions. for more details, refer to the instruction table and figure 7 . i/o pin ra.n(rb.n) data bus buffer output pm0.0 (or pm0.1) pm1.n (or pm2.n) mova r, ra (or mova r, rb) instruction mov ra, r (or mov rb, r) instruction enable enable vdd input/output pin of the ra(rb) figure 7. architecture of ra & rb input/output pins
p reliminary w741c20x publication release date: march 1998 - 15 - revision a3 port mode 0 register (pm0) the port mode 0 register is organized as 4-bit binary register (pm0.0 to pm0.3). pm0 can be used to determine the structure of the input/output ports; it is controlled by the mov pm0, #i instruction. the bit descriptions are as follows: pm0 w 0 1 2 w 3 note: w means write only. bit 0 = 0 ra port is cmos output type. bit 0 = 1 ra port is nmos open drain output type. bit 1 = 0 rb port is cmos output type. bit 0 = 1 rb port is nmos open drain output type. bit 2 & bit 3 are reserved. port mode 1 register (pm1) the port mode 1 register is organized as 4-bit binary register (pm1.0 to pm1.3). pm1 can be used to control the input/output mode of port ra. pm1 is controlled by the mov pm1, #i instruction. the bit descriptions are as follows: pm1 w w w 0 1 2 w 3 note: w means write only. bit 0 = 0 ra.0 works as output pin; bit 0 = 1 ra.0 works as input pin bit 1 = 0 ra.1 works as output pin; bit 1 = 1 ra.1 works as input pin bit 2 = 0 ra.2 works as output pin; bit 2 = 1 ra.2 works as input pin bit 3 = 0 ra.3 works as output pin; bit 3 = 1 ra.3 works as input pin at initial reset, port ra is input mode (pm1 = 1111b). port mode 2 register (pm2) the port mode 2 register is organized as 4-bit binary register (pm2.0 to pm2.3). pm2 can be used to control the input/output mode of port rb. pm2 is controlled by the mov pm2, #i instruction. the bit descriptions are as follows: pm2 w w w 0 1 2 w 3 note: w means write only.
p reliminary w741c20x - 16 - bit 0 = 0 rb.0 works as output pin; bit 0 = 1 rb.0 works as input pin bit 1 = 0 rb.1 works as output pin; bit 1 = 1 rb.1 works as input pin bit 2 = 0 rb.2 works as output pin; bit 2 = 1 rb.2 works as input pin bit 3 = 0 rb.3 works as output pin; bit 3 = 1 rb.3 works as input pin at initial reset, the port rb is input mode (pm2 = 1111b). port mode 3 register (pm3) port mode 3 register is organized as a 4-bit binary register (pm3.0 to pm3.3). pm3 can be used to determine the operating mode of the output port re and the clock rate of the serial i/o function. the pm3 control diagram is shown in figure 8 . the bit descriptions are as follows: w w 0 1 2 3 pm3 note: w means write only. bit 0 is reserved. bit 1 = 0 the output of the port re is the output of the internal parallel port rt. = 1 the port re works as the serial input/output port. bit 2 is reserved. bit 3 = 0 serial tx rate = f osc /2 = 1 serial tx rate = f osc /256 pm3.1 mux. internal parallel port rt port re fosc/2 pm3.3 fosc/256 serial i/o port figure 8. pm3 control diagram
p reliminary w741c20x publication release date: march 1998 - 17 - revision a3 port mode 4 register (pm4) the port mode 4 register is organized as 4-bit binary register (pm4.0 to pm4.3). pm4 can be used to control the input/output mode of port rc. pm4 is controlled by the mov pm4, #i instruction. the bit descriptions are as follows: pm4 w w w 0 1 2 w 3 note: w means write only. bit 0 = 0 rc.0 works as output pin; bit 0 = 1 rc.0 works as input pin bit 1 = 0 rc.1 works as output pin; bit 1 = 1 rc.1 works as input pin bit 2 = 0 rc.2 works as output pin; bit 2 = 1 rc.2 works as input pin bit 3 = 0 rc.3 works as output pin; bit 3 = 1 rc.3 works as input pin at initial reset, port rc is input mode (pm4 = 1111b). port mode 5 register (pm5) the port mode 5 register is organized as 4-bit binary register (pm5.0 to pm5.3). pm5 can be used to control the input/output mode of port rd. pm5 is controlled by the mov pm5, #i instruction. the bit descriptions are as follows: pm5 w w w 0 1 2 w 3 note: w means write only. bit 0 = 0 rd.0 works as output pin; bit 0 = 1 rd.0 works as input pin bit 1 = 0 rd.1 works as output pin; bit 1 = 1 rd.1 works as input pin bit 2 = 0 rd.2 works as output pin; bit 2 = 1 rd.2 works as input pin bit 3 = 0 rd.3 works as output pin; bit 3 = 1 rd.3 works as input pin at initial reset, the port rb is input mode (pm2 = 1111b). input/output ports rc, rd port rc consists of pins rc.0 to rc.3, and port rd consists of pins rd.0 to rd.3. at initial reset, input/output ports rc and rd are both in input mode. when rc and rd are used as output ports, the cmos type is the only ouput driving type. each pin of port rc or rd can be specified as input or output mode independently by the pm4 and pm5 registers. the mova r, rc or mova r, rd instructions operate the input functions and the mov rc, r or mov rd, r operate the output functions. when the pef, hef, and ief corresponding to the rc port are set, a signal change at the specified pins of port rc will execute the hold mode release or interrupt subroutine. port status register 0 (psr0) records the status of port rc, and that can be read out and cleared by the mov r, psr0, and clr psr0 instructions. before the port mode of the rc port is changed from output mode to input mode in the hold mode release and interrupt application, the output value must be preset to the same as the system status to prevent the undesired signal change being accepted.
p reliminary w741c20x - 18 - when the interrupt of rc port is accepted, the corresponding event flag (evf.2) will be reset, but the content of psr0 should not be changed except the clr psr0 or mov pef, #i instruction being executed or performing the reset function. in addition, the falling edge signal on the pin of port rc specified by the instruction mov sef, #i will cause the device to exit the stop mode. the rd port is used as the i/o port only. refer to figure 9 , figure 10 and the instruction table for more details. i/o pin rc.n(rd.n) data bus buffer output pm4.n (or pm5.n) mova r, rc (or mova r, rd) instruction mov rc, r (or mov rd, r) instruction enable enable vdd input/output pin of the rc(rd) figure 9. architecture of rc & rd input/output pins port enable flag (pef) the port enable flag is organized as 4-bit binary register (pef.0 to pef.3). before port rc may be used to release the hold mode or preform interrupt function, the content of the pef must be set first. the pef is controlled by the mov pef, #i instruction. the bit descriptions are as follows: pef w w w 0 1 2 w 3 note: w means write only. pef.0: enable/disable the signal change at pin rc.0 to release hold mode or perform interrupt. pef.1: enable/disable the signal change at pin rc.1 to release hold mode or perform interrupt. pef.2: enable/disable the signal change at pin rc.2 to release hold mode or perform interrupt. pef.3: enable/disable the signal change at pin rc.3 to release hold mode or perform interrupt. port status register 0 (psr0) port status register 0 is organized as 4-bit binary register (psr0.0 to psr0.3). psr0 can be read or cleared by the mova r, psr0, and clr psr0 instructions. the bit descriptions are as follows: r r r r 0 1 2 3 psr0 note: r means read only.
p reliminary w741c20x publication release date: march 1998 - 19 - revision a3 bit 0 = 1 signal change at rc.0 bit 1 = 1 signal change at rc.1 bit 2 = 1 signal change at rc.2 bit 3 = 1 signal change at rc.3 reset clr psr0 hcf.2 int 2 reset clr evf, #i evf.2 hef.2 ief.2 mov pef, #i signal change detector pef.0 data bus pef.3 signal change detector pef.1 signal change detector pef.2 signal change detector d ck q r psr0.0 d ck q r psr0.1 d ck q r psr0.2 d ck q r psr0.3 d ck q r rc.3 rc.2 rc.1 rc.0 sef.0 sef.3 sef.1 sef.2 falling edge detector falling edge detector falling edge detector falling edge detector wake up from stop mode pm4.3 pm4.2 pm4.1 pm4.0 pm4.3 pm4.2 pm4.1 pm4.0 mova r, rc figure 10. input architecture of ports rc output port re output port re can be used as an output of the internal rt port, or as a serial input/output port. the control flow is shown in figure 8 . when bit 1 of port mode 3 register (pm3) equals to 0, port re works as an output of internal port rt. when the mov re, r instruction is executed, the data in the ram will be output to port rt through port re. when re works as a parallel output port, it provides a high sink current to drive leds. when bit 1 of pm3 equals to 1, the re port works as a serial input/output port, and re.0 to re.3 are used as dout, clko, din, and clki, respectively. in this case, the din pin will has a built-in pull-high resistor. the serial i/o functions are controlled by the instructions sop r and sip r. the functions of the two instructions are described below:
p reliminary w741c20x - 20 - (1) when the sip r instruction is executed, the data will be loaded from the serial input buffer to the acc and ram first, and bit 1 of port status register 2 will automatically be set to "1" (busy i = 1). then the clki pin will send out 8 clocks and the data from the din pin will be loaded to sib at the rising edge of the clki pin. after the 8 clocks have been sent, busy i will be reset to "0" and evf.5 will be set to "1." at this time, if ief.5 has been set (ief.5 = 1), an interrupt is executed; if hef.5 has been set (hef.5 = 1), the hold state is terminated. users can check the status of psr2.1 (busy i ) to know whether the serial input process is completed or not. if a serial input process is not completed, and the sip r instruction is executed again, the data will be lost. the timing is shown in figure 11. t1 t2 t3 t4 clki (re3) data latch busyi (psr2.1) evf5 ins. din (re2) sip r 1 2 3 4 5 6 7 8 notes : 1. these clocks at the clki pin are internal clock and its frequency is fosc/2. 2. when the internal signal of the data latch equals to "1," then the data in sib will be loaded into ram and acc. figure 11. timing of the serial input function (sip r) (2) when the sop r instruction is executed, the data will be loaded to the serial output buffer (sob) and bit 3 of port status register 2 will be set to "1" (busy o = 1). then the clko pin will send out 8 clocks and the data in sob will be sent out at the falling edge of the clko pin. after the 8 clocks have been sent, busy o will be reset to "0" and evf.6 will be set to "1." at this time, if ief.6 has been set (ief.6 = 1), an interrupt is executed; if hef.6 has been set (hef.6 = 1), the hold state is terminated. users can check the status of psr2.3 (busy o ) to know whether the serial output process is completed or not. if a serial output process is not completed, and the sop r instruction is executed again, the data will be lost. the timing is shown in figure 12 .
p reliminary w741c20x publication release date: march 1998 - 21 - revision a3 t1 t2 t3 t4 clko (re1) data latch busyo (psr2.3) evf6 ins. dout (re0) sop r 1 2 3 4 5 6 7 8 notes : 1. these clocks at the clko pin are internal clock and its frequency is fosc/2. 2. when the internal signal of the data latch equals to "1," then the data of the ram and acc be loaded to sob. figure 12. timing of the serial output function (sop r) in the above description, the low nibble location of the serial input/output register is contributed to the acc, and the high nibble is to r. the port status register 2 (psr2) including busy i, and busy o can be read out or cleared by the mova r, psr2, or clr psr2 instruction. port status register 2 (psr2) port status register 2 is organized as 4-bit binary register (psr2.0 to psr2.3). psr2 is controlled by the mova r, psr2, and clr psr2 instructions. the bit descriptions are as follows: r r 0 1 2 3 psr2 note: r means read only. bit 0 is reserved. bit 1 (busy i): serial port input busy flag. bit 2 is reserved. bit 3 (busy o): serial port output busy flag.
p reliminary w741c20x - 22 - mfp output pin (mfp) the mfp output pin can output the timer 1 clock or the modulation frequency; the output of the pin is determined by mode register 1 (mr1). the organization of mr1 is shown in figure 6 . when bit 2 of mr1 is reset to "0," the mfp output can deliver a modulation output in any combination of one signal from among dc, 4096hz, 2048hz, and one or more signals from among 128 hz, 64 hz, 8 hz, 4 hz, 2 hz, or 1 hz (when using a 32.768 khz crystal). the mov mfp, #i instruction is used to specify the modulation output combination. the data specified by the 8-bit operand and the mfp output pin are shown as below. (f osc = 32.768 khz) r7 r6 r5 r4 r3 r2 r1 r0 function 0 0 0 0 0 0 low level 0 0 0 0 0 1 128 hz 0 0 0 0 1 0 64 hz 0 0 0 0 0 1 0 0 8 hz 0 0 1 0 0 0 4 hz 0 1 0 0 0 0 2 hz 1 0 0 0 0 0 1 hz 0 0 0 0 0 0 high level 0 0 0 0 0 1 128 hz 0 0 0 0 1 0 64 hz 0 1 0 0 0 1 0 0 8 hz 0 0 1 0 0 0 4 hz 0 1 0 0 0 0 2 hz 1 0 0 0 0 0 1 hz 0 0 0 0 0 0 2048 hz 0 0 0 0 0 1 2048 hz * 128 hz 0 0 0 0 1 0 2048 hz * 64 hz 1 0 0 0 0 1 0 0 2048 hz * 8 hz 0 0 1 0 0 0 2048 hz * 4 hz 0 1 0 0 0 0 2048 hz * 2 hz 1 0 0 0 0 0 2048 hz * 1 hz 0 0 0 0 0 0 4096 hz 0 0 0 0 0 1 4096 hz * 128 hz 0 0 0 0 1 0 4096 hz * 64 hz 1 1 0 0 0 1 0 0 4096 hz * 8 hz 0 0 1 0 0 0 4096 hz * 4 hz 0 1 0 0 0 0 4096 hz * 2 hz 1 0 0 0 0 0 4096 hz * 1 hz
p reliminary w741c20x publication release date: march 1998 - 23 - revision a3 interrupts the w741c20x provides five internal interrupt sources (divider 0, timer 0, timer 1, serial i/o) and two external interrupt sources ( int , port rc). vector addresses for each of the interrupts are located in the range of program memory (rom) addresses 004h to 020h. the flags ief, pef, and evf are used to control the interrupts. when evf is set to "1" by hardware and the corresponding bits of ief and pef have been set by software, an interrupt is generated. when an interrupt occurs, all of the interrupts are inhibited until the en int or mov ief, #i instruction is invoked. the interrupts can also be disabled by executing the dis int instruction. when an interrupt is generated in hold mode, the hold mode will be released momentarily and interrupt subroutine will be executed. after the rtn instruction is executed in an interrupt subroutine, the m c will enter hold mode again. the operation flow chart is shown in figure 14 . the control diagram is shown below. s r q s r q s r q ief.0 ief.1 interrupt process circuit interrupt vector generator 004h 008h 020h ief.7 initial reset clr evf,#i instruction dis int instruction initial reset mov ief,#i enable en int evf.1 evf.0 evf.7 disable divider 0 overflow signal timer 0 underflow signal timer 1 underflow signal figure 13. interrupt event control diagram interrupt enable flag (ief) the interrupt enable flag is organized as an 8-bit binary register (ief.0 to ief.7). these bits are used to control the interrupt conditions. it is controlled by the mov ief, #i instruction. when one of these interrupts is accepted, the corresponding bit of the event flag will be reset, but the other bits are unaffected. in interrupt subroutine, these interrupts will be disabled till the instruction mov ief, #i or en int is executed again. to enable these interrupts, the instructions mov ief, #i or en int must be executed again. otherwise, these interrupts can be disabled by executing dis int instruction. the bit descriptions are as follows: w w w 1 2 3 ief 4 w w 5 6 0 w w 7 note: w means write only.
p reliminary w741c20x - 24 - ief.0 = 1 interrupt 0 is accepted by overflow from the divider 0. ief.1 = 1 interrupt 1 is accepted by underflow from the timer 0. ief.2 = 1 interrupt 2 is accepted by a signal change at port rc. ief.3 is reserved. ief.4 = 1 interrupt 4 is accepted by a falling edge signal at the int pin. ief.5 = 1 interrupt 5 is accepted by the serial port received completely. ief.6 = 1 interrupt 6 is accepted by the serial port transmitted completely. ief.7 = 1 interrupt 7 is accepted by underflow from timer 1. external int the external interrupt int pin contains a pull-up resistor. when the hef.4 or ief.4 flag is set, the falling edge of the int pin will execute the hold mode release or interrupt subroutine. a low level on the int pin will release the stop mode. stop mode operation in stop mode, all operations of the m c cease (including the operation of the oscillator). the m c enters stop mode when the stop instruction is executed and exits stop mode when an external trigger is activated (by a low level on the int pin or a falling signal on the rc port). when the designated signal is accepted, the m c awakens and warms up, and then executes the next instruction. stop mode wake-up enable flag for ports rc (sef) the stop mode wake-up flag for ports rc is organized as a 4-bit binary register (sef.0 to sef.3). before port rc may be used to make the device exit the stop mode, the content of the sef must be set first. the sef is controlled by the mov sef, #i instruction. the bit descriptions are as follows: sef w w w 0 1 2 w 3 note: w means write only. sef 0 = 1 device will exit stop mode when falling edge signal is applied to pin rc.0 sef 1 = 1 device will exit stop mode when falling edge signal is applied to pin rc.1 sef 2 = 1 device will exit stop mode when falling edge signal is applied to pin rc.2 sef 3 = 1 device will exit stop mode when falling edge signal is applied to pin rc.3 hold mode operation in hold mode, all operations of the m c cease, except for the operation of the oscillator and timer. the m c enters hold mode when the hold instruction is executed. the hold mode can be released in one of five ways: by the action of timer 0, timer 1, the divider, the int pin, the rc port. before the device enters the hold mode, the hef, pef, and ief flags must be set to define the hold mode release conditions. for more details, refer to the instruction-set table and the following flow chart.
p reliminary w741c20x publication release date: march 1998 - 25 - revision a3 divider 0, /int, timer 0, timer 1, serial i/o and signal change at rc port in hold mode? ief flag set? pc <- (pc+1) ief flag set? no yes no yes yes no yes no hold hef flag set? reset evf flag execute interrupt service routine reset evf flag execute interrupt service routine interrupt enable? interrupt enable? yes yes no no disable interrupt disable interrupt (note) (note) note: the bit of evf corresponding to the interrupt signal will be reset. figure 14. hold mode and interrupt operation flow chart
p reliminary w741c20x - 26 - hold mode release enable flag (hef) the hold mode release enable flag is organized as an 8-bit binary register (hef.0 to hef.7). the hef is used to control the hold mode release conditions. it is controlled by the mov hef, #i instruction. the bit descriptions are as follows: w 0 1 2 hef w w w w 3 4 5 6 7 w w note: w means write only. hef.0 = 1 overflow from the divider 0 causes hold mode to be released. hef.1 = 1 underflow from timer 0 causes hold mode to be released. hef.2 = 1 signal change at port rc causes hold mode to be released. hef.3 is reserved. hef.4 = 1 falling edge signal at the int pin causes hold mode to be released. hef.5 = 1 the serial port received completely causes hold mode to be released. hef.6 = 1 the serial port transmitted completely causes hold mode to be released. hef.7 = 1 underflow from timer 1 causes hold mode to be released. hold mode release condition flag (hcf) the hold mode release condition flag is organized as a 8-bit binary register (hcf0 to hcf7). it indicates by which interrupt source the hold mode has been released, and is loaded by hardware. the hcf can be read out by the mova r, hcfl and mova r, hcfh instructions. when any of the hcf bits is "1," the hold mode will be released and the hold instruction is invalid. the hcf can be reset by the clr evf or mov hef,#i (hef = 0) instructions. when evf and hef have been reset, the corresponding bit of hcf is reset simultaneously. the bit descriptions are as follows: r r r r hcf 0 1 2 3 4 5 r r r 6 7 note: r means read only. hcf.0 = 1 hold mode was released by overflow from the divider 0 hcf.1 = 1 hold mode was released by underflow from the timer 0 hcf.2 = 1 hold mode was released by a signal change at port rc hcf.3 is reserved. hcf.4 = 1 hold mode was released by a falling edge signal at the int pin hcf.5 = 1 hold mode was released by underflow from the timer 1 hcf.6 = 1 hold mode was released by the serial port received completely. hcf.7 = 1 hold mode was released by the serial port transmitted completely.
p reliminary w741c20x publication release date: march 1998 - 27 - revision a3 event flag (evf) the event flag is organized as a 8-bit binary register (evf0 to evf7). it is set by hardware and reset by clr evf,#i instruction or the occurrence of an interrupt. the bit descriptions are as follows: r r r r evf 0 1 2 3 4 5 r r r 6 7 note: r means read only. evf.0 = 1 overflow from divider 0 occurred. evf.1 = 1 underflow from timer 0 occurred. evf.2 = 1 signal change at port rc occurred. evf.3 is reserved. evf.4 = 1 falling edge signal at the int pin occurred. evf.5 = 1 the serial port received completely. evf.6 = 1 the serial port transmitted completely. evf.7 = 1 underflow from timer 1 occurred. reset function the w741c20x is reset either by a power-on reset or by using the external res pin. the initial state of the w741c20x after the reset function is executed is described below. program counter (pc) 000h tm0, tm1 reset mr0, mr1, page registers reset psr0, psr2, pm3 registers reset ief, hef, hcf, pef, evf, sef flags reset timer 0 input clock f osc /4 timer 1 input clock f osc mfp output low input/output ports ra, rb input mode input/output ports rc, rd input mode output port re high ra and rb ports output type cmos type input clock of the watchdog timer f osc /1024
p reliminary w741c20x - 28 - absolute maximum ratings parameter rating unit supply voltage to ground potential -0.3 to +7.0 v applied input/output voltage -0.3 to +7.0 v power dissipation 120 mw ambient operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc characteristics (v dd -v ss = 3.0v, fosc. = 32.768 khz, ta = 25 c; unless otherwise specified) parameter sym. conditions min. typ. max. unit op. voltage v dd - 2.2 - 5.5 v op. current (crystal type) i op1 no load (ext-v) - 8 20 m a op. current (rc type) i op2 no load (ext-v) - 35 65 m a hold current (crystal type) i hm1 hold mode no load (ext-v) - 4 6 m a hold current (rc type) i hm2 hold mode no load (ext-v) - 16 40 m a stop current (crystal type) i sm1 stop mode no load (ext-v) - 0.1 2 m a stop current (rc type) i sm2 stop mode no load (ext-v) - 0.1 2 m a input low voltage v il - v ss - 0.3 v dd v input high voltage v ih - 0.7 v dd - v dd v mfp output low voltage v ml i ol = 3.5 ma - - 0.4 v mfp output high voltage v mh i oh = -3.5 ma 2.4 - - v port ra, rb sink current i abl v ol = 0.9v 9 - - ma port ra, rb source current i abh v oh = 2.4v 0.4 1.2 - ma port rc, rd output low voltage v cdl i ol = 2.0 ma - - 0.4 v port rc, rd output high voltage v cdh i oh = -2.0 ma 2.4 - - v port re sink current i el v ol = 0.9v 9 - - ma port re source current i eh v oh = 2.4v 0.4 1.2 - ma
p reliminary w741c20x publication release date: march 1998 - 29 - revision a3 dc characteristics, continued parameter sym. conditions min. typ. max. unit int pull-up resistor r int - 50 250 1000 k w din pin pull-up resistor r din re.2 used as serial input pin 50 250 1000 k w res pull-up resistor r res - 20 100 500 k w ac characteristics (v dd -v ss = 3.0 v, ta = 25 c; unless otherwise specified) parameter sym. conditions min. typ. max. unit rc type - - 4000 op. frequency f osc crystal type 1 (option low speed type) - 32.768 - khz crystal type 2 (option high speed type) 400 - 4190 frequency deviation by voltage drop for rc oscillator d f f f(3v) - f(2.4v) f(3v) - - 10 % instruction cycle time t i one machine cycle - 4/f osc - s serial port data ready time t dr - 200 - - ns serial port data hold time t dh - 200 - - ns reset active width t raw f osc = 32.768 khz 1 - - m s interrupt active width t iaw f osc = 32.768 khz 1 - - m s
p reliminary w741c20x - 30 - pad assignment & positions 4 5 6 7 8 9 2580 m 2280 m m m 1 3 2 10 12 13 15 16 (0,0) x y 11 14 29 28 27 17 18 26 25 24 23 22 21 20 19 note: the chip substrate must be connected to system ground (v ss ). pad no. pad name x y pad no. pad name x y 1 ra2 -576.30 943.70 16 rc0 215.10 -965.00 2 ra3 -819.50 943.70 17 rc1 476.30 -965.00 3 int -1063.00 943.70 18 rc2 722.30 -965.00 4 res -1115.00 671.70 19 rc3 1113.90 -959.30 5 v ss -1115.00 464.20 20 v dd 1113.90 -749.30 6 re0 -1115.00 207.00 21 rd0 1113.90 -492.10 7 re1 -1115.00 -21.00 22 rd1 1113.90 -264.10 8 re2 -1115.00 -264.20 23 rd2 1113.90 -20.90 9 re3 -1115.00 -492.20 24 rd3 1113.90 207.10 10 v ss -1115.00 -749.40 25 v dd 1113.90 464.30 11 rb0 -1115.00 -965.00 26 x out 1113.90 738.00 12 rb1 -813.30 -965.00 27 x in 1061.30 943.70 13 rb2 -552.10 -965.00 28 ra0 752.20 943.70 14 rb3 -302.10 -965.00 29 ra1 509.00 943.70 15 mfp -40.90 -965.00
p reliminary w741c20x publication release date: march 1998 - 31 - revision a3 typical application circuit mfp int res xout xin rc2 rc3 ra0 ra3 output signal rb0 rb1 rb2 rb3 rc0 rc1 rd0 rd1 rd2 rd3 or re0 re1 re2 re3 vcc vcc vcc v dd v ss vcc vcc
p reliminary w741c20x - 32 - instruction set table symbol description acc: accumulator acc.n: accumulator bit n wr: working register page: page register mr0: mode register 0 mr1: mode register 1 pm0: port mode 0 pm1: port mode 1 pm2: port mode 2 pm3: port mode 3 pm4: port mode 4 pm5: port mode 5 psr0: port status register 0 psr2: port status register 2 r: memory (ram) of address r r.n: memory bit n of address r i: constant parameter l: branch or jump address cf: carry flag zf: zero flag pc: program counter tm0l: low nibble of the timer 0 counter tm0h: high nibble of the timer 0 counter tm1l: low nibble of the timer 1 counter tm1h: high nibble of the timer 1 counter tabl: low nibble of the look-up table address buffer tabh: high nibble of the look-up table address buffer ief.n: interrupt enable flag n hcf.n: hold mode release condition flag n hef.n: hold mode release enable flag n sef.n: stop mode wake-up enable flag n pef.n: port enable flag n
p reliminary w741c20x publication release date: march 1998 - 33 - revision a3 continued evf.n: event flag n ! =: not equal &: and ^: or ex: exclusive or ? : transfer direction, result [page*10h+()]: contents of address page(bit2, bit1, bit0)*10h+() [p()]: contents of port p instruction set table 1 mnemonic function flag affected cycle arithmetic add r, acc acc ? (r) + (acc) zf, cf 1 add wr, #i acc ? (wr) + i zf, cf 1 addr r, acc acc, r ? (r) + (acc) zf, cf 1 addr wr, #i acc, wr ? (wr) + i zf, cf 1 adc r, acc acc ? (r) + (acc) + (cf) zf, cf 1 adc wr, #i acc ? (wr) + i + (cf) zf, cf 1 adcr r, acc acc, r ? (r) + (acc) + (cf) zf, cf 1 adcr wr, #i acc, wr ? (wr) + i + (cf) zf, cf 1 adu r, acc acc ? (r) + (acc) zf 1 adu wr, #i acc ? (wr) + i zf 1 adur r, acc acc, r ? (r) + (acc) zf 1 adur wr, #i acc, w r ? (wr) + i zf 1 sub r, acc acc ? (r) - (acc) zf, cf 1 sub wr, #i acc ? (wr) - i zf, cf 1 subr r, acc acc, r ? (r) - (acc) zf, cf 1 subr wr, #i acc, wr ? (wr) - i zf, cf 1 sbc r, acc acc ? (r) - (acc) - (cf) zf, cf 1 sbc wr, #i acc ? (wr) - i - (cf) zf, cf 1 sbcr r, acc acc, r ? (r) - (acc) - (cf) zf, cf 1 sbcr wr, #i acc, wr ? (wr) - i - (cf) zf, cf 1
p reliminary w741c20x - 34 - instruction set table 1, continued mnemonic function flag affected cycle inc r acc, r ? (r) + 1 zf, cf 1 dec r acc, r ? (r) - 1 zf, cf 1 logic operations anl r, acc acc ? (r) & (acc) zf 1 anl wr, #i acc ? (wr) & i zf 1 anlr r, acc acc, r ? (r) & (acc) zf 1 anlr w, r #i acc, wr ? (wr) & i zf 1 orl r, acc acc ? (r) (acc) zf 1 orl wr, #i acc ? (wr) i zf 1 orlr r, acc acc, r ? (r) (acc) zf 1 orlr wr, #i acc, wr ? (wr) i zf 1 xrl r, acc acc ? (r) ex (acc) zf 1 xrl wr, #i acc ? (wr) ex i zf 1 xrlr r, acc acc, r ? (r) ex (acc) zf 1 xrlr wr, #i acc, wr ? (wr) ex i zf 1 branch jmp l pc10~pc0 ? l10~l0 1 jb0 l pc10~pc0 ? l10~l0; if acc.0 = "1" 1 jb1 l pc10~pc0 ? l10~l0; if acc.1 = "1" 1 jb2 l pc10~pc0 ? l10~l0; if acc.2 = "1" 1 jb3 l pc10~pc0 ? l10~l0; if acc.3 = "1" 1 jz l pc10~pc0 ? l10~l0; if acc = 0 1 jnz l pc10~pc0 ? l10~l0; if acc ! = 0 1 jc l pc10~pc0 ? l10~l0; if cf = "1" 1 jnc l pc10~pc0 ? l10~l0; if cf != "1" 1 dskz r acc, r ? (r) - 1; skip if acc = 0 zf, cf 1 dsknz r acc, r ? (r) - 1; skip if acc != 0 zf, cf 1 skb0 r skip if r.0 = "1" 1 skb1 r skip if r.1 = "1" 1 skb2 r skip if r.2 = "1" 1 skb3 r skip if r.3 = "1" 1
p reliminary w741c20x publication release date: march 1998 - 35 - revision a3 instruction set table 1, continued mnemonic function flag affected cycle data move mov wr, r wr ? (r) 1 mov r, wr r ? (wr) 1 mova wr, r acc, wr ? (r) zf 1 mova r, wr acc, r ? (wr) zf 1 mov r, acc r ? (acc) 1 mov acc, r acc ? (r) zf 1 mov r, #i r ? i 1 mov wr, @r wr ? [pr(bit2, bit1, bit0)x10h +(r)] 2 mov @r, wr [pr(bit2, bit1, bit0)x10h +(r)] ? wr 2 mov tabl, r tabl ? (r) 1 mov tabh, r tabh ? (r) 1 movc r r ? [tab 10h + (acc) ] 2 movc wr, #i wr ? [(i6 ~ i0) 10h + (acc)] 2 input & output mova r, ra acc, r ? [ra] zf 1 mova r, rb acc, r ? [rb] zf 1 mova r, rc acc, r ? [rc] zf 1 mova r, rd acc, r ? [rd] zf 1 mov ra, r [ra] ? (r) 1 mov rb, r [rb] ? (r) 1 mov rc, r [rc] ? (r) 1 mov rd, r [rd] ? (r) 1 mov re, r [re] ? (r) 1 sop r re0 ? (r), (acc); re1 ? clk 1 sip r r, acc ? sib; re3 ? clk 2 mov mfp, #i [mfp] ? i 1 flag & register mova r, page acc, r ? page (page register) zf 1 mov page, r page ? (r) 1 mov mr0, #i mr0 ? i 1 mov mr1, #i mr1 ? i 1
p reliminary w741c20x - 36 - instruction set table 1, continued mnemonic function flag affected cycle mov page, #i page ? i 1 mova r, cf acc.0, r.0 ? cf zf 1 mov cf, r cf ? (r.0) cf 1 mova r, hcfl acc, r ? hcf0~hcf3 zf 1 mova r, hcfh acc, r ? hcf4~hcf7 zf 1 clr pmf, #i clear parameter flag if in = 1 1 set pmf, #i set parameter flag if in = 1 1 mov pm0, #i port mode 0 ? i 1 mov pm1, #i port mode 1 ? i 1 mov pm2, #i port mode 2 ? i 1 mov pm3, #i port mode 3 ? i 1 mov pm4, #i port mode 4 ? i 1 mov pm5, #i port mode 5 ? i 1 clr evf, #i clear event flag if in = 1 1 mov pef, #i set/reset port enable flag 1 mov ief, #i set/reset interrupt enable flag 1 mov hef, #i set/reset hold mode release enable flag 1 mov sef, #i set/reset stop mode wake-up enable flag for rc port 1 mova r, psr0 acc, r ? port status register 0 zf 1 clr psr0 clear port status register 0 1 mova r, psr2 acc, r ? port status register 2 zf 1 clr psr2 clear port status register 2 1 set cf set carry flag cf 1 clr cf clear carry flag cf 1 clr divr0 clear the last 4-bit of the divider 0 1 clr wdt clear watchdog timer 1
p reliminary w741c20x publication release date: march 1998 - 37 - revision a3 instruction set table 1, continued mnemonic function flag affected cycle shift & rotate shrc r acc.n, r.n ? (r.n +1 ); acc.3, r.3 ? 0; cf ? r.0 zf, cf 1 rrc r acc.n, r.n ? (r.n +1 ); acc.3, r.3 ? cf; cf ? r.0 zf, cf 1 shlc r acc.n, r.n ? (r.n -1 ); acc.0, r.0 ? 0; cf ? r.3 zf, cf 1 rlc r acc.n, r.n ? (r.n -1 ); acc.0, r.0 ? cf; cf ? r.3 zf, cf 1 timer mov tm0l, r tm0l ? (r) 1 mov tm0h, r tm0h ? (r) 1 mov tm0, #i timer 0 set 1 mov tm1l, r tm1l ? (r) 1 mov tm1h, r tm1h ? (r) 1 mov tm1, #i timer 1 set 1 subroutine call l stack ? (pc)+1; pc10 ~ pc0 ? l10 ~ l0 1 rtn (pc) ? stack 1 other hold enter hold mode 1 stop enter stop mode 1 nop no operation 1 en int enable interrupt function 1 dis int disable interrupt function 1
p reliminary w741c20x - 38 - instruction set table 2 adc r, acc add r to acc with cf machine code: machine cycle: operation: description: flag affected: 0 0 0 1 0 0 0 0 r6 r5 r4 r3 r2 r1 r0 0 1 acc ? (r) + (acc) + (cf) the contents of the data memory location addressed by r6 to r0, acc, and cf are binary added and the result is loaded into the acc. cf & zf adc wr, #i add immediate data to wr with cf machine code: machine cycle: operation: description: flag affected: 0 0 0 0 1 1 0 0 i3 i2 i1 i0 w3 w2 w1 w0 1 acc ? (wr) + i + (cf) the contents of the working register (wr), i and cf are binary added and the result is loaded into the acc. cf & zf adcr r, acc add r to acc with cf machine code: machine cycle: operation: description: flag affected: 0 0 0 1 0 0 1 0 r6 r5 r4 r3 r2 r1 r0 0 1 acc, r ? (r) + (acc) + (cf) the contents of the data memory location addressed by r6 to r0, acc, and cf are binary added and the result is placed in the acc and the data memory. cf & zf
p reliminary w741c20x publication release date: march 1998 - 39 - revision a3 instruction set table 2, continued adcr wr, #i add immediate data to wr with cf machine code: machine cycle: operation: description: flag affected: 0 0 0 0 1 1 0 1 i3 i2 i1 i0 w3 w2 w1 w0 1 acc, wr ? (wr) + i + (cf) the contents of the working register (wr), i, cf are binary added and the result is placed in the acc and the wr. cf & zf add r, acc add r to acc machine code: machine cycle: operation: description: flag affected: 0 0 1 1 0 0 0 0 r6 r5 r4 r3 r2 r1 r0 0 1 acc ? (r) + (acc) the contents of the data memory location addressed by r6 to r0 and acc are binary added and the result is loaded into the acc. cf & zf add wr, #i add immediate data to wr machine code: machine cycle: operation: description: flag affected: 0 0 0 1 1 1 0 0 i3 i2 i1 i0 w3 w2 w1 w0 1 acc ? (wr) + i the contents of the working register (wr) and the immediate data i are binary added and the result is loaded into the acc. cf & zf
p reliminary w741c20x - 40 - instruction set table 2, continued addr r, acc add r to acc machine code: machine cycle: operation: description: flag affected: 0 0 1 1 0 0 1 0 r6 r5 r4 r3 r2 r1 r0 0 1 acc, r ? (r) + (acc) the contents of the data memory location addressed by r6 to r0 and acc are binary added and the result is placed in the acc and the data memory. cf & zf addr wr, #i add immediate data to wr machine code: machine cycle: operation: description: flag affected: 0 0 0 1 1 1 0 1 i3 i2 i1 i0 w3 w2 w1 w0 1 acc, wr ? (wr) + i the contents of the working register (wr) and the immediate data i are binary added and the result is placed in the acc and the wr. cf & zf adu r, acc add r to acc and carry flag unchange machine code: machine cycle: operation: description: flag affected: 0 0 1 0 1 0 0 0 0 r6 r5 r4 r3 r2 r1 r0 1 acc ? (r) + (acc) the contents of the data memory location addressed by r6 to r0 and acc are binary added and the result is loaded into the acc. zf
p reliminary w741c20x publication release date: march 1998 - 41 - revision a3 instruction set table 2, continued adu wr, #i add immediate data to wr and carry flag unchange machine code: machine cycle: operation: description: flag affected: 0 0 1 0 1 1 0 0 i3 i2 i1 i0 w3 w2 w1 w0 1 acc ? (wr) + i the contents of the working register (wr) and the immediate data i are binary added and the result is loaded into the acc. zf adur r, acc add r to acc and carry flag unchange machine code: machine cycle: operation: description: flag affected: 0 0 1 0 1 0 0 1 0 r6 r5 r4 r3 r2 r1 r0 1 acc, r ? (r) + (acc) the contents of the data memory location addressed by r6 to r0 and acc are binary added and the result is placed in the acc and the data memory. zf adur wr, #i add immediate data to wr and carry flag unchange machine code: machine cycle: operation: description: flag affected: 0 0 1 0 1 1 0 1 i3 i2 i1 i0 w3 w2 w1 w0 1 acc, wr ? (wr) + i the contents of the working register (wr) and the immediate data i are binary added and the result is placed in the wr and the acc. zf
p reliminary w741c20x - 42 - instruction set table 2, continued anl r, acc and r to acc machine code: machine cycle: operation: description: flag affected: 0 0 1 0 1 0 1 0 0 r6 r5 r4 r3 r2 r1 r0 1 acc ? (r) & (acc) the contents of the data memory location addressed by r6 to r0 and the acc are anded and the result is loaded into the acc. zf anl wr, #i and immediate data to wr machine code: machine cycle: operation: description: flag affected: 0 0 1 0 1 1 1 0 i3 i2 i1 i0 w3 w2 w1 w0 1 acc ? (wr) & i the contents of the working register (wr) and the immediate data i are anded and the result is loaded into the acc. zf anlr r, acc and r to acc machine code: machine cycle: operation: description: flag affected: 0 0 1 0 1 0 1 1 0 r6 r5 r4 r3 r2 r1 r0 1 acc, r ? (r) & (acc) the contents of the data memory location addressed by r6 to r0 and the acc are anded and the result is placed in the data memory and the acc. zf
p reliminary w741c20x publication release date: march 1998 - 43 - revision a3 instruction set table 2, continued anlr wr, #i and immediate data to wr machine code: machine cycle: operation: description: flag affected: 0 0 1 0 1 1 1 1 i3 i2 i1 i0 w3 w2 w1 w0 1 acc, wr ? (wr) & i the contents of the working register (wr) and the immediate data i are anded and the result is placed in the wr and the acc. zf call l call subroutine machine code: machine cycle: operation: description: 0 1 1 0 0 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 1 stack ? (pc)+1; pc10 ~ pc0 ? l10 ~ l0 the next program counter (pc10 to pc0) is saved in the stack and then the direct address (l10 to l0) is loaded into the program counter. a subroutine is called. clr cf clear cf machine code: machine cycle: operation: description: flag affected: 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 clear cf clear carry flag to 0. cf
p reliminary w741c20x - 44 - instruction set table 2, continued clr divr0 reset the last 4 bits of the divider 0 machine code: machine cycle: operation: description: 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 1 reset the last 4 bits of the divider 0 when this instruction is executed, the last 4 bits of the divider 0 (14 bits) are reset. clr evf, #i clear event flag machine code: machine cycle: operation: description: 0 1 0 0 0 0 0 0 i7 i6 i5 i4 i3 i2 i1 i0 1 clear event flag the condition corresponding to the data specified by i7 to i0 is controlled. i0~i7 mode after execution of instruction i0 = 1 evf0 caused by overflow from the divider 0 is reset. i1 = 1 i2 = 1 i7 = 1 evf1 caused by underflow from the timer 0 is reset. evf2 caused by the signal change at port rc is reset. evf4 caused by the falling edge signal on int pin is reset. i4 = 1 evf7 caused by underflow from the timer 1 is reset. i3 reserved i5 = 1 i6 = 1 evf5 caused by the serial port received completely. evf6 caused by the serial port transmitted completely.
p reliminary w741c20x publication release date: march 1998 - 45 - revision a3 instruction set table 2, continued clr pmf, #i clear parameter flag machine code: machine cycle: operation: description: 0 0 0 1 0 1 1 0 1 0 0 0 i3 i2 i1 i0 1 clear parameter flag description of each flag: i0, i1, i2 : reserved i3 = 1 : the input clock of the watchdog timer is fosc/1024. clr psr0 clear port status register 0 (rc port signal change flag) machine code: machine cycle: operation: description: 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 clear port status register 0 (rc port signal change flag) when this instruction is executed, the rc port signal change flag (psr0) is cleared. clr psr2 clear port status register 2 (serial port status flags) machine code: machine cycle: operation: description: 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 clear port status register 2 (serial port status flags) when this instruction is executed, the serial port status flags (psr2) are cleared. clr wdt reset the last 4 bits of the watchdog timer machine code: machine cycle: operation: description: 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 1 reset the last 4 bits of the watchdog timer when this instruction is executed, the last 4 bits of the watchdog timer are reset.
p reliminary w741c20x - 46 - instruction set table 2, continued dec r decrement r content machine code: machine cycle: operation: description: flag affected: 0 1 0 0 1 0 1 0 1 r6 r5 r4 r3 r2 r1 r0 1 acc, r ? (r) - 1 decrement the data memory content and load result into the acc and the data memory. cf & zf dis int disable interrupt function machine code: machine cycle: operation: description: 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 disable interrupt function interrupt function is inhibited by executing this instruction. dsknz r decrement r content then skip if acc ! = 0 machine code: machine cycle: operation: description: flag affected: 0 1 0 0 1 0 0 0 1 r6 r5 r4 r3 r2 r1 r0 1 acc, r ? (r) - 1; pc ? (pc) + 2 if acc ! = 0 decrement the data memory content and load result into the acc and the data memory. if acc ! = 0, the program counter is incremented by 2 and produces a skip. cf & zf
p reliminary w741c20x publication release date: march 1998 - 47 - revision a3 instruction set table 2, continued dskz r decrement r content then skip if acc is zero machine code: machine cycle: operation: description: flag affected: 0 1 0 0 1 0 0 0 0 r6 r5 r4 r3 r2 r1 r0 1 acc, r ? (r) - 1; pc ? (pc) + 2 if acc = 0 decrement the data memory content and load result into the acc and the data memory. if acc = 0, the program counter is incremented by 2 and produces a skip. cf & zf en int enable interrupt function machine code: machine cycle: operation: description: 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 enable interrupt function this instruction enables the interrupt function. hold enter the hold mode machine code: machine cycle: operation: description: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 enter the hold mode the following two conditions cause the hold mode to be released. (1) an interrupt is accepted. (2) the hold release condition specified by the hef is met. in hold mode, when an interrupt is accepted the hold mode will be released and the interrupt service routine will be executed. after completing the interrupt service routine by executing the rtn instruction, the m c will enter hold mode again.
p reliminary w741c20x - 48 - instruction set table 2, continued inc r increment r content machine code: machine cycle: operation: description: flag affected: 0 1 0 0 1 0 1 0 0 r6 r5 r4 r3 r2 r1 r0 1 acc, r ? (r) + 1 increment the data memory content and load the result into the acc and the data memory. cf & zf jb0 l jump when bit 0 of acc is "1" machine code: machine cycle: operation: description: 1 0 0 0 0 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 1 pc10 ~ pc0 ? l10 ~ l0; if acc.0 = "1" if bit 0 of the acc is "1," pc10 to pc0 of the program counter are replaced with the data specified by l10 to l0 and a jump occurs. if bit 0 of the acc is "0," the program counter (pc) is incremented. jb1 l jump when bit 1 of acc is "1" machine code: machine cycle: operation: description: 1 0 0 1 0 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 1 pc10 ~ pc0 ? l10 ~ l0; if acc.1 = "1" if bit 1 of the acc is "1," pc10 to pc0 of the program counter are replaced with the data specified by l10 to l0 and a jump occurs. if bit 1 of the acc is "0," the program counter (pc) is incremented. jb2 l jump when bit 2 of acc is "1" machine code: machine cycle: operation: description: 1 0 1 0 0 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 1 pc10 ~ pc0 ? l10 ~ l0; if acc.2="1" if bit 2 of the acc is "1," pc10 to pc0 of the program counter are replaced with the data specified by l10 to l0 and a jump occurs. if bit 2 of the acc is "0," the program counter (pc) is incremented.
p reliminary w741c20x publication release date: march 1998 - 49 - revision a3 instruction set table 2, continued jb3 l jump when bit 3 of acc is "1" machine code: machine cycle: operation: description: 1 0 1 1 0 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 1 pc10 ~ pc0 ? l10 ~ l0; if acc.3 = "1" if bit 3 of the acc is "1," pc10 to pc0 of the program counter are replaced with the data specified by l10 to l0 and a jump occurs. if bit 3 of the acc is "0," the program counter (pc) is incremented. jc l jump when cf is "1" machine code: machine cycle: operation: description: 1 1 1 1 0 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 1 pc10 ~ pc0 ? l10 ~ l0; if cf = "1" if cf is "1," pc10 to pc0 of the program counter are replaced with the data specified by l10 to l0 and a jump occurs. if the cf is "0," the program counter (pc) is incremented. jmp l jump absolutely machine code: machine cycle: operation: description: 0 1 1 1 0 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 1 pc10 ~ pc0 ? l10 ~ l0 pc10 to pc0 of the program counter are replaced with the data specified by l10 to l0 and an unconditional jump occurs.
p reliminary w741c20x - 50 - instruction set table 2, continued jnc l jump when cf is not "1" machine code: machine cycle: operation: description: 1 1 0 1 0 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 1 pc10 ~ pc0 ? l10 ~ l0; if cf = "0" if cf is "0," pc10 to pc0 of the program counter are replaced with the data specified by l10 to l0 and a jump occurs. if cf is "1," the program counter (pc) is incremented. jnz l jump when acc is not zero machine code: machine cycle: operation: description: 1 1 0 0 0 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 1 pc10 ~ pc0 ? l10 ~ l0; if acc ! = 0 if the acc is not zero, pc10 to pc0 of the program counter are replaced with the data specified by l10 to l0 and a jump occurs. if the acc is zero, the program counter (pc) is incremented. jz l jump when acc is zero machine code: machine cycle: operation: description: 1 1 1 0 0 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 1 pc10 ~ pc0 ? l10 ~ l0; if acc = 0 if the acc is zero, pc10 to pc0 of the program counter are replaced with the data specified by l10 to l0 and a jump occurs. if the acc is not zero, the program counter (pc) is incremented.
p reliminary w741c20x publication release date: march 1998 - 51 - revision a3 instruction set table 2, continued mov acc, r move r content to acc machine code: machine cycle: operation: description: 0 1 0 0 1 1 1 0 1 r6 r5 r4 r3 r2 r1 r0 1 acc ? (r) the contents of the data memory location addressed by r6 to r0 are loaded into the acc. zf mov cf, r move r.0 content to cf machine code: machine cycle: operation: description: flag affected: 0 1 0 1 1 0 0 0 0 r6 r5 r4 r3 r2 r1 r0 1 cf ? (r.0) the bit 0 content of the data memory location addressed by r6 to r0 is loaded into cf. cf
p reliminary w741c20x - 52 - instruction set table 2, continued mov hef, #i set/reset hold mode release enable flag machine code: machine cycle: operation: description: 0 1 0 0 0 0 0 1 i7 i6 i5 i4 i3 i2 i1 i0 1 hold mode release enable flag control i0~i7 operation i0 = 1 i1 = 1 i2 = 1 i4 = 1 i5 = 1 the hef2 is set so that signal change at port rc caused the hold mode to be released. the hef0 is set so that overflow from the divider 0 caused the hold mode to be released. the hef1 is set so that underflow from the timer 0 caused the hold mode to be released. i7 = 1 the hef4 is set so that the falling edge signal at the int pin caused the hold mode to be released. the hef7 is set so that underflow from the timer 1 caused the hold mode to be released. i3 reserved i6 = 1 the hef6 is set so that the serial port transmitted completely caused the hold mode to be released. the hef5 is set so that the serial port received completely caused the hold mode to be released.
p reliminary w741c20x publication release date: march 1998 - 53 - revision a3 instruction set table 2, continued mov ief, #i set/reset interrupt enable flag machine code: machine cycle: operation: description: 0 1 0 1 0 0 0 1 i7 i6 i5 i4 i3 i2 i1 i0 1 interrupt enable flag control the interrupt enable flag corresponding to the data specified by i7 - i0 is controlled: i0~i7 operation i0 = 1 i1 = 1 i2 = 1 i4 = 1 i5 = 1 the ief0 is set so that interrupt 0 (overflow from the divider 0) is accepted. the ief1 is set so that interrupt 1 (underflow from the timer 0) is accepted. the ief2 is set so that interrupt 2 (signal change at port rc) is accepted. the ief4 is set so that interrupt 4 (falling edge signal at the int pin) is accepted. i7 = 1 the ief5 is set so that interrupt 5 (the serial port received completely) is accepted. the ief7 is set so that interrupt 7 (underflow from the timer 1) is accepted. i3 reserved the ief6 is set so that interrupt 6 (the serial port transmitted completely) is accepted. i6 = 1
p reliminary w741c20x - 54 - instruction set table 2, continued mov mfp, #i modulation frequency pulse generator machine code: machine cycle: operation: description: 0 0 0 1 0 0 1 i7 i6 i5 i4 i3 i2 i1 i0 0 1 [mfp] ? i if the bit 2 of mr1 is "0," the waveform specified by i7 to i0 is delivered at the mfp output pin (mfp). the relation between the waveform and immediate data i is shown as follows: i5~i0 i0 = 1 i1 = 1 i2 = 1 i3 = 1 i4 = 1 i5 = 1 signal fosc 256 fosc 512 fosc 4096 fosc 8192 fosc 16384 fosc 32768 i7 i6 signal 0 0 1 1 0 1 0 1 low high fosc/16 fosc/8 mov mr0, #i load immediate data to mode register 0 (mr0) machine code: machine cycle: operation: description: 0 0 0 1 0 0 1 1 1 0 0 0 i3 i2 i1 i0 1 mr0 ? i the immediate data i are loaded to the mr0. mr0 bits description: bit 0 = 0 timer 0 stop down-counting = 1 timer 0 start down-counting = 0 the fundamental frequency of timer 0 is fosc/4 = 1 the fundamental frequency of timer 0 is fosc/1024 reserved bit 1 bit 2 bit 3 reserved
p reliminary w741c20x publication release date: march 1998 - 55 - revision a3 instruction set table 2, continued mov mr1, #i load immediate data to mode register 1 (mr1) machine code: machine cycle: operation: description: 0 0 0 1 0 0 1 1 0 0 0 0 i3 i2 i1 i0 1 mr1 ? i the immediate data i are loaded to the mr1. mr1 bit description: bit0 = 1 the internal fundamental frequency of timer 1 is fosc/64 = 0 the internal fundamental frequency of timer 1 is fosc = 0 the fundamental frequency source of timer 1 is internal clock = 1 the fundamental frequency source of timer 1 is external clock via rc.0 input pin = 0 the specified waveform of the mfp generator is delivered at the mfp output pin = 1 the specified frequency of the timer 1 is delivered at the mfp output pin bit1 bit2 bit3 = 0 timer 1 stop down-counting = 1 timer 1 start down-counting
p reliminary w741c20x - 56 - instruction set table 2, continued mov page, #i load immediate data to page register machine code: machine cycle: operation: description: 0 1 0 1 0 1 1 0 1 0 0 0 i3 i2 i1 i0 1 page register ? i the immediate data i are loaded to the pr. bit 3 is reserved. bit 0, bit 1, and bit 2 indirect addressing mode preselect bits: bit1 bit0 0 0 1 1 0 1 0 1 = page 0 (00h~0fh) = page 1 (10h~1fh) = page 2 (20h~2fh) = page 3 (30h~3fh) bit2 0 0 0 0 0 0 1 1 0 1 0 1 = page 4 (40h~4fh) = page 5 (50h~5fh) = page 6 (60h~6fh) = page 7 (70h~7fh) 1 1 1 1 mov pef, #i set/reset port enable flag machine code: machine cycle: operation: description: 0 1 0 0 0 0 1 1 0 0 0 0 i3 i2 i1 i0 1 port enable flag control the data specified by i can cause hold mode to be released or an interrupt to occur. the signal change on port rc is specified. i0~i7 i0 = 1 i1 = 1 i2 = 1 i3 = 1 signal change at port rc rc0 rc1 rc2 rc3
p reliminary w741c20x publication release date: march 1998 - 57 - revision a3 instruction set table 2, continued mov pm0, #i set/reset port mode 0 register machine code: machine cycle: operation: description: 0 1 0 1 0 0 1 1 0 0 0 0 i2 i1 i0 i3 1 set/reset port mode 0 register i0 = 0: ra port is cmos type; i0 = 1: ra port is nmos type. i1 = 0: rb port is cmos type; i1 = 1: rb port is nmos type. i2 = 0: rc port pull-high resistor is disabled; i2 = 1: rc port pull-high resistor is enabled. i3 = 0: rd port pull-high resistor is disabled; i3 = 1: rd port pull-high resistor is enabled. mov pm1, #i ra port independent input/output control machine code: machine cycle: operation: description: 0 1 0 1 0 1 1 1 0 0 0 0 i3 i2 i1 i0 1 ra port 4 pins input/output control is independent. i0 = 0: ra.0 is output pin; i0 = 1: ra.0 is input pin. i1 = 0: ra.1 is output pin; i1 = 1: ra.1 is input pin. i2 = 0: ra.2 is output pin; i2 = 1: ra.2 is input pin. i3 = 0: ra.3 is output pin; i3 = 1: ra.3 is input pin. default condition ra port is input mode (pm = 1111b). mov pm2, #i rb port independent input/output control machine code: machine cycle: operation: description: 0 1 0 1 0 1 1 1 1 0 0 0 i3 i2 i1 i0 1 rb port 4 pins input/output control is independent. i0 = 0: rb.0 is output pin; i0 = 1: rb.0 is input pin. i1 = 0: rb.1 is output pin; i1 = 1: rb.1 is input pin. i2 = 0: rb.2 is output pin; i2 = 1: rb.2 is input pin. i3 = 0: rb.3 is output pin; i3 = 1: rb.3 is input pin. default condition rb port is input mode (pm2 = 1111b).
p reliminary w741c20x - 58 - instruction set table 2, continued mov pm3, #i set/reset port mode 3 register machine code: machine cycle: operation: description: 0 1 0 1 0 1 1 0 0 0 0 0 i2 i1 i0 i3 1 set/reset port mode 3 register i0 is reserved. i1 = 0: the port re is used as the output of the internal parallel port rt. i1 = 1: the port re works as the serial input/output port. i2 is reserved. i3 = 0: serial tx rate = f osc /2 i3 = 1: serial tx rate = f osc /256 mov pm4, #i rc port independent input/output control machine code: machine cycle: operation: description: 0 0 1 1 0 1 1 1 0 0 0 0 i3 i2 i1 i0 1 rc port 4 pins input/output control is independent. i0 = 0: rc.0 is output pin; i0 = 1: rc.0 is input pin. i1 = 0: rc.1 is output pin; i1 = 1: rc.1 is input pin. i2 = 0: rc.2 is output pin; i2 = 1: rc.2 is input pin. i3 = 0: rc.3 is output pin; i3 = 1: rc.3 is input pin. default condition rc port is input mode (pm4 = 1111b). mov pm5, #i rd port independent input/output control machine code: machine cycle: operation: description: 0 0 1 1 0 1 1 1 1 0 0 0 i3 i2 i1 i0 1 rd port 4 pins input/output control is independent. i0 = 0: rd.0 is output pin; i0 = 1: rd.0 is input pin. i1 = 0: rd.1 is output pin; i1 = 1: rd.1 is input pin. i2 = 0: rd.2 is output pin; i2 = 1: rd.2 is input pin. i3 = 0: rd.3 is output pin; i3 = 1: rd.3 is input pin. default condition rd port is input mode (pm5 = 1111b).
p reliminary w741c20x publication release date: march 1998 - 59 - revision a3 instruction set table 2, continued mov r, acc move acc content to r machine code: machine cycle: operation: description: 0 1 0 1 1 0 0 1 1 r6 r5 r4 r3 r2 r1 r0 1 r ? (acc) the contents of the acc are loaded to the data memory location addressed by r6 to r0. mova r, ra input ra port data to acc & r machine code: machine cycle: operation: description: flag affected: 0 1 0 1 1 0 1 1 0 r6 r5 r4 r3 r2 r1 r0 1 acc , r ? [ra] the data on port ra are loaded into the data memory location addressed by r6 to r0 and the acc. zf mova r, rb input rb port data to acc & r machine code: machine cycle: operation: description: flag affected: 0 1 0 1 1 0 1 1 1 r6 r5 r4 r3 r2 r1 r0 1 acc , r ? [rb] the data on port rb are loaded into the data memory location addressed by r6 to r0 and the acc. zf
p reliminary w741c20x - 60 - instruction set table 2, continued mova r, rc input rc port data to acc & r machine code: machine cycle: operation: description: flag affected: 0 1 0 0 1 0 1 1 0 r6 r5 r4 r3 r2 r1 r0 1 acc , r ? [rc] the input data on the input port rc are loaded into the data memory location addressed by r6 to r0 and the acc. zf mova r, rd input rd port data to acc & r machine code: machine cycle: operation: description: flag affected: 0 1 0 0 1 0 1 1 1 r6 r5 r4 r3 r2 r1 r0 1 acc , r ? [rd] the input data on the input port rd are loaded into the data memory location addressed by r6 to r0 and the acc. zf mov r, wr move wr content to r machine code: machine cycle: operation: description: 1 1 1 1 1 w3 w2 w1 w0 r6 r5 r4 r3 r2 r1 r0 1 r ? (wr) the contents of the wr are loaded to the data memory location addressed by r6 to r0.
p reliminary w741c20x publication release date: march 1998 - 61 - revision a3 instruction set table 2, continued mov r, #i load immediate data to r machine code: machine cycle: operation: description: 1 0 1 1 1 i3 i2 i1 i0 r6 r5 r4 r3 r2 r1 r0 1 r ? i the immediate data i are loaded to the data memory location addressed by r6 to r0. mov ra, r output r content to ra port machine code: machine cycle: operation: description: 0 1 0 1 1 0 1 0 0 r6 r5 r4 r3 r2 r1 r0 1 [ra] ? (r) the data in the data memory location addressed by r6 to r0 are output to the port ra. mov rb, r output r content to rb port machine code: machine cycle: operation: description: 0 1 0 1 1 0 1 0 1 r6 r5 r4 r3 r2 r1 r0 1 [rb] ? (r) the contents of the data memory location addressed by r6 to r0 are output to the port rb. mov rc, r output r content to rc port machine code: machine cycle: operation: description: 1 0 0 0 1 1 0 0 0 r6 r5 r4 r3 r2 r1 r0 1 [rc] ? (r) the data in the data memory location addressed by r6 to r0 are output to the port rc.
p reliminary w741c20x - 62 - instruction set table 2, continued mov rd, r output r content to rd port machine code: machine cycle: operation: description: 1 0 0 0 1 1 0 0 1 r6 r5 r4 r3 r2 r1 r0 1 [rd] ? (r) the contents of the data memory location addressed by r6 to r0 are output to the port rd. mov re, r output r content to port re machine code: machine cycle: operation: description: 0 1 0 1 1 1 1 0 0 r6 r5 r4 r3 r2 r1 r0 1 [re] ? (r) the contents of the data memory location addressed by r6 to r0 are output to port re. mov sef, #i set/reset stop mode waked-up enable flag for port rc machine code: machine cycle: operation: description: 0 1 0 1 0 0 1 0 0 0 0 0 i3 i2 i1 i0 1 set/reset stop mode wake-up enable flag for port rc the data specified by i cause a wake-up from the stop mode. the falling- edge signal on port rc can be specified independently. i0~i7 i0 = 1 i1 = 1 i2 = 1 i3 = 1 falling edge signal at port rc rc0 rc1 rc2 rc3
p reliminary w741c20x publication release date: march 1998 - 63 - revision a3 instruction set table 2, continued mov tm0, #i timer 0 set machine code: machine cycle: operation: description: 0 0 0 1 0 0 0 0 i7 i6 i5 i4 i3 i2 i1 i0 1 timer 0 set the data specified by i7 to i0 is loaded to the timer 0 to start the timer. mov tm0l, r move r content to tm0l machine code: machine cycle: operation: description: 0 0 0 1 0 1 0 0 0 r6 r5 r4 r3 r2 r1 r0 1 tm0l ? (r) the content of the data memory location addressed by r6 to r0 are loaded into the tm0l. mov tm0h, r move r content to tm0h machine code: machine cycle: operation: description: 0 0 0 1 0 1 0 0 1 r6 r5 r4 r3 r2 r1 r0 1 tm0h ? (r) the content of the data memory location addressed by r6 to r0 are loaded into the tm0h. mov tm1, #i timer 1 set machine code: machine cycle: operation: description: 0 0 0 1 0 0 0 1 i7 i6 i5 i4 i3 i2 i1 i0 1 timer 1 set the data specified by i7 to i0 is loaded to the timer 1 to start the timer.
p reliminary w741c20x - 64 - instruction set table 2, continued mov tm1l, r move r content to tm1l machine code: machine cycle: operation: description: 0 0 0 1 0 1 0 1 0 r6 r5 r4 r3 r2 r1 r0 1 tm1l ? (r) the content of the data memory location addressed by r6 to r0 are loaded into the tm1l. mov tm1h, r move r content to tm1h machine code: machine cycle: operation: description: 0 0 0 1 0 1 0 1 1 r6 r5 r4 r3 r2 r1 r0 1 tm1h ? (r) the content of the data memory location addressed by r6 to r0 are loaded into the tm1h. mov wr, r move r content to wr machine code: machine cycle: operation: description: 1 1 1 0 1 w3 w2 w1 w0 r6 r5 r4 r3 r2 r1 r0 1 wr ? (r) the contents of the data memory location addressed by r6 to r0 are loaded to the wr. mov wr, @r indirect load from r to wr machine code: machine cycle: operation: description: 1 1 0 0 1 w3 w2 w1 w0 r6 r5 r4 r3 r2 r1 r0 2 wr ? [pr (bit2, bit1, bit0) 10h + (r)] the data memory contents of address [pr (bit2, bit1, bit0) 10h + (r)] are loaded to the wr.
p reliminary w741c20x publication release date: march 1998 - 65 - revision a3 instruction set table 2, continued mov @r, wr indirect load from wr to r machine code: machine cycle: operation: description: 1 1 0 1 1 w3 w2 w1 w0 r6 r5 r4 r3 r2 r1 r0 2 [pr (bit2, bit1, bit0) 10h + (r)] ? wr the contents of the wr are loaded to the data memory location addressed by [pr (bit2, bit1, bit0) 10h + (r)] . mov page, r move r content to page register machine code: machine cycle: operation: description: 0 1 0 1 1 1 1 0 1 r6 r5 r4 r3 r2 r1 r0 1 pr ? (r) the contents of the data memory location addressed by r6 to r0 are loaded to the pr. mova r, cf move cf content to acc.0 & r.0 machine code: machine cycle: operation: description: flag affected: 0 1 0 1 1 0 0 1 0 r6 r5 r4 r3 r2 r1 r0 1 acc.0, r.0 ? (cf) the content of cf is loaded to bit 0 of the data memory location addressed by r6 to r0 and the acc. the other bits of the data memory and acc are reset to "0." zf
p reliminary w741c20x - 66 - instruction set table 2, continued mova r, hcfh move hcf4~7 to acc & r machine code: machine cycle: operation: description: flag affected: 0 1 0 0 1 0 0 1 1 r6 r5 r4 r3 r2 r1 r0 1 acc, r ? hcf4~7 the contents of hcf bit 4 to bit 7 (hcf4 to hcf7) are loaded to the data memory location addressed by r6 to r0 and the acc. the acc contents and the meaning of the bits after execution of this instruction are as follows: bit 0 bit 1 bit 3 bit 2 hcf4: "1" when the hold mode is released by the falling edge signal at the int pin. hcf5: "1" when the hold mode is released by underflow from timer 1. hcf6: "1" when the hold mode is released by the serial port receiving completely. hcf7: "1" when the hold mode is released by the serial port transmitting completely. zf mova r, hcfl move hcf0~3 to acc & r machine code: machine cycle: operation: description: flag affected: 0 1 0 0 1 0 0 1 0 r6 r5 r4 r3 r2 r1 r0 1 acc, r ? hcf0~3 the contents of hcf bit 0 to bit 3 (hcf0 to hcf3) are loaded to the data memory location addressed by r6 to r0 and the acc. the acc contents and the meaning of the bits after execution of this instruction are as follows: bit 0 bit 1 bit 3 bit 2 hcf0: "1" when the hold mode is released by overflow from the divider 0. hcf2: "1" when the hold mode is released by a signal change on port rc. hcf1: "1" when the hold mode is released by underflow from timer 0. reserved. zf
p reliminary w741c20x publication release date: march 1998 - 67 - revision a3 instruction set table 2, continued mova r, page move page register content to acc & r machine code: machine cycle: operation: description: flag affected: 0 1 0 1 1 1 1 1 1 r6 r5 r4 r3 r2 r1 r0 1 acc , r ? (page register) the contents of the page register (pr) are loaded to the data memory location addressed by r6 to r0 and the acc. zf mova r, psr0 move port status register 0 content to acc & r machine code: machine cycle: operation: description: flag affected: 0 1 0 0 1 1 1 1 0 r6 r5 r4 r3 r2 r1 r0 1 acc, r ? rc port signal change flag (psr0) the contents of the rc port signal change flag (psr0) are loaded to the data memory location addressed by r6 to r0 and the acc. when the signal changes on any pin of the rc port, the corresponding signal change flag should be set to 1. otherwise, it should be 0. zf mova r, psr2 move port status register 0 content to acc & r machine code: machine cycle: operation: description: flag affected: 0 1 0 1 1 1 1 1 0 r6 r5 r4 r3 r2 r1 r0 1 acc, r ? serial i/o port status flags (psr2) the contents of the serial i/o port status flags (psr2) are loaded to the data memory location addressed by r6 to r0 and the acc. zf
p reliminary w741c20x - 68 - instruction set table 2, continued mova r, wr move wr content to acc & r machine code: machine cycle: operation: description: flag affected: 0 1 1 1 1 w3 w2 w1 w0 r6 r5 r4 r3 r2 r1 r0 1 acc, r ? (wr) the contents of the wr are loaded to the acc and the data memory location addressed by r6 to r0. zf mova wr, r move r content to acc & wr machine code: machine cycle: operation: description: flag affected: 0 1 1 0 1 w3 w2 w1 w0 r6 r5 r4 r3 r2 r1 r0 1 acc, wr ? (r) the contents of the data memory location addressed by r6 to r0 are loaded to the wr and the acc. zf mov tabl, r move r content to tabl machine code: machine cycle: operation: description: 1 0 0 1 1 0 0 0 0 r6 r5 r4 r3 r2 r1 r0 1 tabl ? (r) the content of the data memory location addressed by r6 to r0 are loaded into the tabl. mov tabh, r move r content to tabh machine code: machine cycle: operation: description: 1 0 0 1 1 0 0 0 1 r6 r5 r4 r3 r2 r1 r0 1 tabh ? (r) the content of the data memory location addressed by r6 to r0 are loaded into the tabh.
p reliminary w741c20x publication release date: march 1998 - 69 - revision a3 instruction set table 2, continued movc r move look-up table rom addressed by tabl and tabh to r machine code: machine cycle: operation: description: 1 0 0 1 1 0 0 1 0 r6 r5 r4 r3 r2 r1 r0 2 wr ? [(tabh) 10h + (tabl)] the contents of the look-up table rom location addressed by tabh and tabl are loaded to r. nop no operation machine code: machine cycle: operation: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 no operation orl r, acc or r to acc machine code: machine cycle: operation: description: flag affected: 0 0 1 1 1 0 1 0 0 r6 r5 r4 r3 r2 r1 r0 1 acc ? (r) (acc) the contents of the data memory location addressed by r6 to r0 and the acc are ored and the result is loaded into the acc. zf orl wr , #i or immediate data to wr machine code: machine cycle: operation: description: flag affected: 0 0 1 1 1 1 1 0 i3 i2 i1 i0 w3 w2 w1 w0 1 acc ? (wr) i the contents of the working register (wr) and the immediate data i are ored and the result is loaded into the acc. zf
p reliminary w741c20x - 70 - instruction set table 2, continued orlr r, acc or r to acc machine code: machine cycle: operation: description: flag affected: 0 0 1 1 1 0 1 1 0 r6 r5 r4 r3 r2 r1 r0 1 acc, r ? (r) (acc) the contents of the data memory location addressed by r6 to r0 and the acc are ored and the result is placed in the data memory and the acc. zf orlr wr , #i or immediate data to wr machine code: machine cycle: operation: description: flag affected: 0 0 1 1 1 1 1 1 i3 i2 i1 i0 w3 w2 w1 w0 1 acc, wr ? (wr) i the contents of the working register(wr) and the immediate data i are ored and the result is placed in the wr and the acc. zf rlc r rotate left r with cf machine code: machine cycle: operation: description: flag affected: 0 1 0 0 1 1 0 0 1 r6 r5 r4 r3 r2 r1 r0 1 acc.n, r.n ? (r.n-1); acc.0, r.0 ? cf; cf ? r.3 the contents of the acc and the data memory location addressed by r6 to r0 are rotated left one bit, bit 3 is rotated into cf, and cf rotated into bit 0 (lsb). the same contents are loaded into the acc. cf & zf
p reliminary w741c20x publication release date: march 1998 - 71 - revision a3 instruction set table 2, continued rrc r rotate right r with cf machine code: machine cycle: operation: description: flag affected: 0 1 0 0 1 1 0 1 1 r6 r5 r4 r3 r2 r1 r0 1 acc.n, r.n ? (r.n+1); acc.3, r.3 ? cf; cf ? r.0 the contents of the acc and the data memory location addressed by r6 to r0 are rotated right one bit, bit 0 is rotated into cf, and cf is rotated into bit 3 (msb). the same contents are loaded into the acc. cf & zf rtn return from subroutine machine code: machine cycle: operation: description: 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 (pc) ? stack the program counter (pc10 to pc0) is restored from the stack. a return from a subroutine occurs. sbc r, acc subtract acc from r with borrow machine code: machine cycle: operation: description: flag affected: 0 0 0 1 0 1 0 0 r6 r5 r4 r3 r2 r1 r0 0 1 acc ? (r) - (acc) - (cf) the contents of the acc and cf are binary subtracted from the contents of the data memory location addressed by r6 to r0 and the result is loaded into the acc. cf & zf
p reliminary w741c20x - 72 - instruction set table 2, continued sbc wr, #i subtract immediate data from wr with borrow machine code: machine cycle: operation: description: flag affected: 0 0 0 0 1 1 1 0 i3 i2 i1 i0 w3 w2 w1 w0 1 acc ? (wr) - i - (cf) the immediate data i and cf are binary subtracted from the contents of the wr and the result is loaded into the acc. cf & zf sbcr r, acc subtract acc from r with borrow machine code: machine cycle: operation: description: flag affected: 0 0 0 1 0 1 1 0 r6 r5 r4 r3 r2 r1 r0 0 1 acc, r ? (r) - (acc) - (cf) the contents of the acc and cf are binary subtracted from the contents of the data memory location addressed by r6 to r0 and the result is placed in the acc and the data memory. cf & zf sbcr wr, #i subtract immediate data from wr with borrow machine code: machine cycle: operation: description: flag affected: 0 0 0 0 1 1 1 1 i3 i2 i1 i0 w3 w2 w1 w0 1 acc, r ? (wr) - i - (cf) the immediate data i and cf are binary subtracted from the contents of the wr and the result is placed in the acc and the wr. cf & zf
p reliminary w741c20x publication release date: march 1998 - 73 - revision a3 instruction set table 2, continued set cf set cf machine code: machine cycle: operation: description: flag affected: 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 set cf set carry flag to 1. cf set pmf, #i set parameter flag machine code: machine cycle: operation: description: 0 0 0 1 0 1 1 0 0 0 0 0 i3 i2 i1 i0 1 set parameter flag description of each flag: i0, i1, i2 : reserved i3 = 1 : the input clock of the watchdog timer is fosc/16384. shlc r shift left r with cf and lsb = 0 machine code: machine cycle: operation: description: flag affected: 0 1 0 0 1 1 0 0 0 r6 r5 r4 r3 r2 r1 r0 1 acc.n, r.n ? (r.n-1); acc.0, r.0 ? 0; cf ? r.3 the contents of the acc and the data memory location addressed by r6 to r0 are shifted left one bit, but bit 3 is shifted into cf, and bit 0 (lsb) is replaced with "0." the same contents are loaded into the acc. cf & zf
p reliminary w741c20x - 74 - instruction set table 2, continued shrc r shift right r with cf and msb = 0 machine code: machine cycle: operation: description: flag affected: 0 1 0 0 1 1 0 1 0 r6 r5 r4 r3 r2 r1 r0 1 acc.n, r.n ? (r.n+1); acc.3, r.3 ? 0; cf ? r.0 the contents of the acc and the data memory location addressed by r6 to r0 are shifted right one bit, but bit 0 is shifted into cf, and bit 3 (msb) is replaced with "0." the same contents are loaded into the acc. cf & zf skb0 r if bit 0 of r is equal to 1 then skip machine code: machine cycle: operation: description: 1 0 0 0 1 0 0 0 0 r6 r5 r4 r3 r2 r1 r0 1 pc ? (pc) + 2; if r.0 = 1 ?1 ? if bit 0 of r is equal to 1, the program counter is incremented by 2 and a skip is produced. if bit 0 of r is not equal to 1, the program counter (pc) is incremented. skb1 r if bit 1 of r is equal to 1 then skip machine code: machine cycle: operation: description: 1 0 0 0 1 0 0 0 1 r6 r5 r4 r3 r2 r1 r0 1 pc ? (pc) + 2; if r.1 = 1 ?1 ? if bit 1 of r is equal to 1, the program counter is incremented by 2 and a skip is produced. if bit 1 of r is not equal to 1, the program counter (pc) is incremented.
p reliminary w741c20x publication release date: march 1998 - 75 - revision a3 instruction set table 2, continued skb2 r if bit 2 of r is equal to 1 then skip machine code: machine cycle: operation: description: 1 0 0 0 1 0 1 0 0 r6 r5 r4 r3 r2 r1 r0 1 pc ? (pc) + 2; if r.2 = 1 ?1 ? if bit 2 of r is equal to 1, the program counter is incremented by 2 and a skip is produced. if bit 2 of r is not equal to 1. the program counter (pc) is incremented. skb3 r if bit 3 of r is equal to 1 then skip machine code: machine cycle: operation: description: 1 0 0 0 1 0 1 0 1 r6 r5 r4 r3 r2 r1 r0 1 pc ? (pc) + 2; if r.3 = 1 ?1 ? if bit 3 of r is equal to 1, the program counter is incremented by 2 and a skip is produced. if bit 3 of r is not equal to 1, the program counter (pc) is incremented. stop enter the stop mode machine code: machine cycle: operation: description: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 stop oscillator device enters stop mode. when the falling edge signal of rc port is accepted, the m c will wake up and execute the next instruction.
p reliminary w741c20x - 76 - instruction set table 2, continued sub r, acc subtract acc from r machine code: machine cycle: operation: description: flag affected: 0 0 1 1 0 1 0 0 r6 r5 r4 r3 r2 r1 r0 0 1 acc ? (r) - (acc) the contents of the acc are binary subtracted from the contents of the data memory location addressed by r6 to r0 and the result is loaded into the acc. cf & zf sub wr , #i subtract immediate data from wr machine code: machine cycle: operation: description: flag affected: 0 0 0 1 1 1 1 0 i3 i2 i1 i0 w3 w2 w1 w0 1 acc ? (wr) - i the immediate data i are binary subtracted from the contents of the wr and the result is loaded into the acc. cf & zf subr r, acc subtract acc from r machine code: machine cycle: operation: description: flag affected: 0 0 1 1 0 1 1 0 r6 r5 r4 r3 r2 r1 r0 0 1 acc, r ? (r) - (acc) the contents of the acc are binary subtracted from the contents of the data memory location addressed by r6 to r0 and the result is placed in the acc and the data memory. cf & zf
p reliminary w741c20x publication release date: march 1998 - 77 - revision a3 instruction set table 2, continued subr wr, #i subtract immediate data from wr machine code: machine cycle: operation: description: flag affected: 0 0 0 1 1 1 1 1 i3 i2 i1 i0 w3 w2 w1 w0 1 acc, wr ? (wr) - i the immediate data i are binary subtracted from the contents of the wr and the result is placed in the acc and the wr. cf & zf xrl r, acc exclusive or r to acc machine code: machine cycle: operation: description: flag affected: 0 0 1 1 1 0 0 0 0 r6 r5 r4 r3 r2 r1 r0 1 acc ? (r) ex (acc) the contents of the data memory location addressed by r6 to r0 and the acc are exclusive-ored and the result is loaded into the acc. zf xrl wr, #i exclusive or immediate data to wr machine code: machine cycle: operation: description: flag affected: 0 0 1 1 1 1 0 0 i3 i2 i1 i0 w3 w2 w1 w0 1 acc ? (wr) ex i the contents of the working register (wr) and the immediate data i are exclusive-ored and the result is loaded into the acc. zf
p reliminary w741c20x - 78 - instruction set table 2, continued xrlr r, acc exclusive or r to acc machine code: machine cycle: operation: description: flag affected: 0 0 1 1 1 0 0 1 0 r6 r5 r4 r3 r2 r1 r0 1 acc, r ? (r) ex (acc) the contents of the data memory location addressed by r6 to r0 and the acc are exclusive-ored and the result is placed in the data memory and the acc. zf xrlr wr, #i exclusive or immediate data to wr machine code: machine cycle: operation: description: flag affected: 0 0 1 1 1 1 0 1 i3 i2 i1 i0 w3 w2 w1 w0 1 acc, wr ? (wr) ex i the contents of the working register(wr) and the immediate data i are exclusive-ored and the result is placed in the wr and the acc. zf
p reliminary w741c20x publication release date: march 1998 - 79 - revision a3 package dimensions 18l pdip-300mil 1.63 1.47 0.064 0.058 symbol min. nom max. max. nom min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.060 1.52 0.175 4.45 0.010 0.125 0.016 0.130 0.018 0.135 0.022 3.18 0.41 0.25 3.30 0.46 3.43 0.56 0.008 0.120 0.375 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.255 0.250 0.245 6.48 6.35 6.22 9.53 7.62 7.37 7.87 0.300 0.290 0.310 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 0.900 0.910 22.86 23.11 0 15 0.055 1.40 0.355 0.335 8.51 9.02 15 0 seating plane a e 2 a c e base plane 1 a 1 e l a s 1 e d 1 b b 18 10 1 9 \ \
p reliminary w741c20x - 80 - 20l pdip 1.63 1.47 0.064 0.058 symbol min. nom max. max. nom min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.060 1.52 0.175 4.45 0.010 0.125 0.016 0.130 0.018 0.135 0.022 3.18 0.41 0.25 3.30 0.46 3.43 0.56 0.008 0.120 0.375 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.255 0.250 0.245 6.48 6.35 6.22 9.53 7.62 7.37 7.87 0.300 0.290 0.310 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 1.026 1.040 20.06 26.42 0 15 0.075 1.91 0.355 0.335 8.51 9.02 15 0 seating plane a e 2 a c e base plane 1 a 1 e l a s 1 e d 1 b b 20 1 10 11 \ \
p reliminary w741c20x publication release date: march 1998 - 81 - revision a3 28-lead p-dip skinny 1.63 1.47 0.064 0.058 symbol min. nom max. max. nom min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.060 1.52 0.175 4.45 0.010 0.125 0.016 0.130 0.018 0.135 0.022 3.18 0.41 0.25 3.30 0.46 3.43 0.56 0.008 0.120 0.370 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.293 0.288 0.283 7.44 7.32 7.19 9.40 7.87 7.62 8.13 0.310 0.300 0.320 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.388 1.400 35.26 35.56 0 15 0.055 1.40 0.350 0.330 8.38 8.89 15 0 e a a c e 1 e d 28 15 1 14 a base plane mounting plane 1 a 1 e l a s 1 b b 2
p reliminary w741c20x - 82 - 20l sop-300mil l o c e h a1 a e b d seating plane y 0.25 gauge plane e 1 20 11 10 7.60 0.32 0.51 0.30 e c b a1 7.40 0.23 0.33 0.10 0.299 0.013 0.020 0.012 0.291 0.009 0.013 0.004 max. dimension in mm 2.65 a symbol min. 2.35 dimension in inches 0.104 min. 0.093 max. control demensions are in milmeters . 1.27 0.10 10.65 l q y h 0 8 0.40 10.00 e 1.27 bsc 0.050 0.004 0.419 0 0.016 0.394 8 0.050 bsc e d 12.60 13.00 0.496 0.512
p reliminary w741c20x publication release date: march 1998 - 83 - revision a3 28l sop-300mil l o c e h a1 a e b d seating plane y 0.25 gauge plane e 1 28 15 14 7.60 0.32 0.51 0.30 e c b a1 7.40 0.23 0.33 0.10 0.299 0.013 0.020 0.012 0.291 0.009 0.013 0.004 max. dimension in mm 2.65 a symbol min. 2.35 dimension in inches 0.104 min. 0.093 max. control demensions are in milmeters . 1.27 0.10 10.65 l q y h 0 8 0.40 10.00 e 1.27 bsc 0.050 0.004 0.419 0 0.016 0.394 8 0.050 bsc e d 17.70 18.10 0.697 0.713
p reliminary w741c20x - 84 - notes: headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792766 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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